High‐Temperature and High‐Electron Mobility Metal‐Oxide‐Semiconductor Field‐Effect Transistors Based on N‐Type Diamond
At a Glance
Section titled “At a Glance”| Metadata | Details |
|---|---|
| Publication Date | 2024-01-19 |
| Journal | Advanced Science |
| Authors | Meiyong Liao, Huanying Sun, Satoshi Koizumi |
| Institutions | Beijing Academy of Quantum Information Sciences, National Institute for Materials Science |
| Citations | 45 |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: N-Type Diamond MOSFETs
Section titled “Technical Documentation & Analysis: N-Type Diamond MOSFETs”This document analyzes the research detailing the development of high-temperature, high-electron mobility n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) based on phosphorus-doped Single Crystal Diamond (SCD). This breakthrough is critical for realizing diamond Complementary Metal-Oxide-Semiconductor (CMOS) circuits for extreme environments.
Executive Summary
Section titled “Executive Summary”This research successfully demonstrates high-performance n-channel diamond MOSFETs, addressing a key challenge in diamond CMOS development.
- Record Mobility: Achieved a field-effect electron mobility of approximately 150 cm2 V-1 s-1 at 573 K (300 °C), the highest reported among n-channel wide-bandgap semiconductors at high temperatures.
- CMOS Enabler: The successful development of high-mobility n-MOSFETs enables the realization of all-diamond CMOS integrated circuits, essential for high-power electronics and integrated spintronics.
- Material Quality: Utilized electronic-grade Phosphorus (P)-doped (111) SCD epilayers grown via step-flow MPCVD, resulting in atomically flat surfaces (average roughness Ra ≈0.1 nm).
- Precise Doping Control: Demonstrated precise control over P-doping concentration across a dual-layer structure, ranging from lightly doped (≈1017 cm-3) for the channel to heavily doped (≈1020 cm-3) for Ohmic contacts.
- High-Temperature Operation: Devices exhibit stable operation and marked current increase (four orders of magnitude increase in drain current) when heated from room temperature to 573 K.
- Fast Switching: Demonstrated a switching speed (rise/decay time) of less than 5 µs at 573 K, suitable for high-frequency mixed-signal circuits and radiation detectors.
Technical Specifications
Section titled “Technical Specifications”The following hard data points were extracted from the experimental results:
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Peak Field-Effect Mobility | ~150 | cm2 V-1 s-1 | Measured at 573 K (300 °C) |
| Maximum Operating Temperature | 573 | K | High-temperature stability demonstrated |
| N- Channel Thickness | 600 | nm | Lightly P-doped epilayer |
| N+ Contact Layer Thickness | 100 | nm | Heavily P-doped epilayer |
| N- Phosphorus Concentration (ND) | ~1017 | cm-3 | Channel doping level |
| N+ Phosphorus Concentration | ~1020 | cm-3 | Ohmic contact doping level |
| Gate Oxide Material / Thickness | Al2O3 / 30 | nm | Deposited via ALD at 473 K |
| Surface Roughness (Ra) | ~0.1 | nm | Atomically flat terrace (Step-flow growth) |
| Switching Speed (Rise/Decay Time) | < 5 | µs | Measured at Vds = 15 V, 573 K |
| Source/Drain Metalization Stack | Ti/Pt/Au | N/A | 50 nm Ti / 10 nm Pt / 60 nm Au |
| Gate Metalization Stack | Ti/Au | N/A | 10 nm Ti / 60 nm Au |
Key Methodologies
Section titled “Key Methodologies”The high-quality n-type diamond epilayers and subsequent MOSFETs were fabricated using the following critical steps:
- Substrate Selection: Used type-Ib (111) High-Pressure High-Temperature (HPHT) diamond substrates with a 3° misorientation to promote the step-flow lateral growth mode.
- MPCVD Growth (N- Layer): A 600 nm lightly P-doped n- epilayer (channel) was grown directly on the HPHT substrate using Microwave Plasma Chemical Vapor Deposition (MPCVD).
- Recipe Parameters: Pressure: 100 Torr; Microwave Power: 500 W; Substrate Temperature: 920 °C.
- MPCVD Growth (N+ Layer): A 100 nm heavily P-doped n+ layer (Ohmic contact) was deposited using a homemade MPCVD reactor to enhance P incorporation efficiency.
- Doping Parameters: Methane concentration: 0.05%; Phosphorus to Carbon (P/C) ratio: 10,000 ppm.
- Ohmic Contact Formation: Source (S) and Drain (D) contacts (Ti/Pt/Au) were deposited on the n+ layer via electron beam deposition and annealed at 773 K for 30 minutes in high vacuum.
- Mesa Etching: The top n+ layer between the S and D electrodes was selectively etched using oxygen plasma Reactive Ion Etching (RIE) to expose the n- channel layer.
- Gate Oxide Deposition: A 30 nm Al2O3 gate oxide was deposited via Atomic Layer Deposition (ALD) at 473 K.
- Gate Metalization: A Ti (10 nm)/Au (60 nm) stack was deposited to form the gate electrode.
6CCVD Solutions & Capabilities
Section titled “6CCVD Solutions & Capabilities”The successful replication and extension of this groundbreaking n-MOSFET research rely heavily on high-quality, precisely engineered SCD materials and advanced fabrication services. 6CCVD is uniquely positioned to supply the necessary components and expertise.
Applicable Materials
Section titled “Applicable Materials”To replicate or advance this research, engineers require electronic-grade, highly controlled SCD material.
| Material Requirement | 6CCVD Solution | Relevance to Research |
|---|---|---|
| Electronic Grade SCD | Single Crystal Diamond (SCD) wafers grown via MPCVD, optimized for electronic applications. | Provides the high-purity, low-defect material necessary for high-mobility devices (comparable to the quality achieved in Figure 1D). |
| Specific Orientation | Custom (111) SCD Substrates and epilayers available. | The (111) orientation is critical for achieving the step-flow growth mode and atomically flat surfaces required for high-performance n-type doping. |
| CMOS Integration | Boron-Doped Diamond (BDD) and Intrinsic SCD. | While this paper focuses on n-type (P-doped), 6CCVD supplies high-quality BDD for the complementary p-channel MOSFETs required to build full diamond CMOS circuits. |
Customization Potential
Section titled “Customization Potential”6CCVD’s in-house capabilities directly address the precise dimensional and material requirements of advanced diamond device fabrication.
- Thickness Control: We offer precise control over epilayer thickness for both SCD and PCD materials, ranging from 0.1 µm up to 500 µm. This capability easily accommodates the 600 nm (0.6 µm) channel and 100 nm contact layers used in this study.
- Substrate Supply: We provide high-quality diamond substrates up to 10 mm thick, suitable for use as the base HPHT material.
- Ultra-Low Roughness Polishing: The research emphasizes the need for an atomically flat surface (Ra ≈0.1 nm). 6CCVD guarantees Ra < 1 nm for our SCD wafers, ensuring the electronic-grade surface quality required for step-flow growth and high-mobility channels.
- Custom Metalization Stacks: The device utilized complex Ti/Pt/Au and Ti/Au stacks. 6CCVD offers internal metalization services, including deposition of Au, Pt, Pd, Ti, W, and Cu, allowing researchers to prototype custom Ohmic and gate contacts without external processing.
- Custom Dimensions: While this device used microscale geometries, 6CCVD can supply plates and wafers up to 125 mm in diameter (PCD), enabling scaling for high-volume manufacturing or large-area sensor arrays.
Engineering Support
Section titled “Engineering Support”Developing next-generation diamond electronics, especially those involving complex doping and high-temperature operation, requires specialized knowledge.
- Expert Consultation: 6CCVD maintains an in-house team of PhD-level material scientists ready to assist with material selection, doping strategies (e.g., optimizing BDD concentration for p-MOSFETs to complement this n-MOSFET research), and surface preparation techniques.
- Application Focus: We provide dedicated engineering support for projects targeting High-Power Electronics, Integrated Spintronics (NV centers), and Extreme Environment Sensors, applications directly enabled by this n-MOSFET breakthrough.
- Global Logistics: We offer reliable global shipping (DDU default, DDP available) to ensure rapid delivery of custom materials to research facilities worldwide.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
Abstract Diamond holds the highest figure‐of‐merits among all the known semiconductors for next‐generation electronic devices far beyond the performance of conventional semiconductor silicon. To realize diamond integrated circuits, both n‐ and p‐channel conductivity are required for the development of diamond complementary metal‐oxide‐semiconductor (CMOS) devices, as those established for semiconductor silicon. However, diamond CMOS has never been achieved due to the challenge in n‐type channel MOS field‐effect transistors (MOSFETs). Here, electronic‐grade phosphorus‐doped n‐type diamond epilayer with an atomically flat surface based on step‐flow nucleation mode is fabricated. Consequently, n‐channel diamond MOSFETs are demonstrated. The n‐type diamond MOSFETs exhibit a high field‐effect mobility around 150 cm 2 V −1 s −1 at 573 K, which is the highest among all the n‐channel MOSFETs based on wide‐bandgap semiconductors. This work enables the development of energy‐efficient and high‐reliability CMOS integrated circuits for high‐power electronics, integrated spintronics, and extreme sensors under harsh environments.