Single-Electron Transistor Operation of a Physically Defined Silicon Quantum Dot Device Fabricated by Electron Beam Lithography Employing a Negative-Tone Resist
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2023-06-01 |
| Journal | IEICE Transactions on Electronics |
| Authors | Shimpei Nishiyama, Kimihiko Kato, Yongxun Liu, Raisei Mizokuchi, Jun Yoneda |
| Institutions | Tokyo Institute of Technology, National Institute of Advanced Industrial Science and Technology |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: Single-Electron Transistor Operation in Nanoscale Silicon QDs
Section titled âTechnical Documentation & Analysis: Single-Electron Transistor Operation in Nanoscale Silicon QDsâExecutive Summary
Section titled âExecutive SummaryâThis research successfully demonstrates the fabrication and operation of physically defined Silicon Quantum Dots (QDs) acting as Single-Electron Transistors (SETs) at cryogenic temperatures (3.8 K). The methodology employed advanced nanoscale patterning techniques directly relevant to the integration challenges faced by solid-state quantum computing platforms.
- Core Achievement: Successful SET operation verified by observing Coulomb diamonds at 3.8 K, validating the fabrication process for integrated silicon qubits.
- Nanoscale Patterning: Utilized negative-tone Electron Beam (EB) lithography (ma-N2401) to achieve critical dimensions, including a 19 nm constriction width.
- Surface Engineering: A two-step thermal oxidation process was implemented to significantly reduce Line Edge Roughness (LER) and shrink the effective QD diameter from 46 nm to 40 nm.
- Electrical Performance: Measured charging energies (Ec) ranging from 7.5 to 18.0 meV, corresponding to total capacitances (C) of 9 to 21 aF.
- Integration Focus: The process is designed for high compatibility with advanced CMOS integration, paving the way for large-scale quantum processors.
- 6CCVD Value Proposition: The challenges addressed (LER, nanoscale integration, cryogenic operation) are directly mitigated by 6CCVDâs superior Single Crystal Diamond (SCD) platform, offering unmatched material purity and surface quality for next-generation solid-state qubits.
Technical Specifications
Section titled âTechnical SpecificationsâThe following hard data points were extracted from the experimental results and fabrication parameters:
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Operating Temperature | 3.8 | K | Electrical characterization (SET operation) |
| SOI Layer Thickness | 40 | nm | Starting material thickness |
| Gate Oxide Thickness | 3 | nm | Formed by 2nd thermal oxidation |
| Final QD Diameter (SEM) | 40 | nm | Physically observed diameter |
| Final Constriction Width | 19 | nm | Narrowest feature size achieved |
| EB Acceleration Voltage | 130 | kV | Lithography parameter |
| EB Base Dose (ma-N2401) | 416 | ”C/cm2 | Exposure dose for QD patterning |
| Oxidation Temperature | 850 | °C | 1st and 2nd thermal oxidation steps |
| Charging Energy (Ec) Range | 7.5 - 18.0 | meV | Observed from Coulomb diamonds |
| Total Capacitance (C) Range | 9 - 21 | aF | Estimated from charging energy |
| Alpha Factor (Lever Arm) Range | 0.017 - 0.058 | eV/V | Side gate tunability (CSG/C) |
Key Methodologies
Section titled âKey MethodologiesâThe fabrication process focused on achieving high-resolution, low-defect nanoscale patterns suitable for quantum device integration, utilizing negative-tone EB lithography and advanced thermal processing.
- Substrate Preparation: SOI wafer (40 nm Si, 145 nm BOX) surface cleaned using diluted Hydrofluoric Acid (HF).
- Resist Processing: Negative-tone resist (ma-N2401) coated, baked (140 °C), and pre-baked (110 °C).
- EB Lithography: Exposure performed at 130 kV with Proximity Effect Correction (PEC) to define QD and constriction patterns.
- Development & Etching: Pattern developed using Tetramethylammonium Hydroxide (TMAH 2.38%, 1 min). Silicon layer etched via Inductive-Coupled Plasma Reactive-Ion-Etching (ICP-RIE) using HBr, O2, and Ar gas mixture.
- Two-Step Thermal Oxidation (LER Reduction):
- 1st Oxidation: Sacrificial oxidation (3 nm at 850 °C) to remove surface damage caused by the dry etching process.
- Oxide Removal: Sacrificial oxide removed using diluted HF.
- 2nd Oxidation: Final thermal oxidation (3 nm at 850 °C) to further improve Line Edge Roughness (LER) and precisely shrink the QD dimensions (46 nm to 40 nm).
- Gate and Doping: CVD-SiO2 and polysilicon deposited for the top gate (100 nm), followed by P+ ion implantation (10 keV) for source/drain definition.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThe research highlights the critical need for ultra-precise material control, low defectivity, and nanoscale patterningâchallenges where 6CCVDâs MPCVD diamond materials offer significant advantages over silicon. Diamond is the superior host material for many solid-state qubits (e.g., NV centers, SiV centers) due to its exceptional thermal properties and long spin coherence times.
| Research Requirement / Challenge | 6CCVD Solution & Capability | Applicable Materials |
|---|---|---|
| Defect Reduction & LER Control: The paper required complex two-step thermal oxidation (850 °C) to reduce LER and surface defects. | 6CCVD provides Optical Grade SCD with as-grown or polished surfaces achieving Ra < 1 nm, minimizing defects and simplifying the integration process by eliminating high-temperature sacrificial steps. | Optical Grade SCD Wafers (Ra < 1 nm Polishing) |
| Advanced Qubit Host Material: Need for a platform with superior coherence time and thermal management for integrated quantum circuits. | 6CCVD specializes in High Purity Single Crystal Diamond (SCD), the ideal material for hosting solid-state qubits, offering superior performance at cryogenic temperatures (3.8 K). | High Purity SCD (0.1 ”m to 500 ”m thickness) |
| Custom Nanoscale Device Integration: The device required precise patterning and integration of gates and contacts compatible with cryogenic operation. | 6CCVD offers in-house custom metalization (Au, Pt, Pd, Ti, W, Cu) and precise laser cutting services, enabling the fabrication of complex gate structures and contacts required for SETs and qubit readout. | SCD/PCD with Custom Metal Stacks |
| Large-Scale Processor Development: The goal is integration with classical peripheral control circuits on large chips. | 6CCVD supports scaling with Polycrystalline Diamond (PCD) wafers up to 125 mm in diameter, providing robust, large-area substrates for high-density quantum device prototyping and manufacturing. | Large Area PCD Substrates (up to 125 mm) |
| Conductive Components: Need for highly conductive, robust materials for cryogenic electrodes and sensors (e.g., charge sensors). | 6CCVD supplies Boron-Doped Diamond (BDD) films, which exhibit metallic conductivity and are chemically inert, perfect for stable cryogenic contacts and integrated sensing elements. | Heavy Boron Doped PCD |
6CCVDâs in-house PhD engineering team possesses deep expertise in material selection and integration for quantum computing, high-power electronics, and advanced sensor applications. We can assist researchers in transitioning from silicon-based prototypes to high-performance diamond platforms, ensuring optimal material specifications (thickness, doping, surface finish) for projects requiring extreme precision and cryogenic stability.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.