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Influence of Different Surface Morphologies on the Performance of High-Voltage, Low-Resistance Diamond Schottky Diodes

MetadataDetails
Publication Date2020-05-07
JournalIEEE Transactions on Electron Devices
AuthorsPhilipp Reinke, Fouad Benkhelifa, Lutz Kirste, Heiko Czap, Lucas Pinti
InstitutionsSonova (Switzerland), Fraunhofer Institute for Applied Solid State Physics
Citations19
AnalysisFull AI Review Included

Technical Documentation & Analysis: High Voltage Diamond Schottky Diodes

Section titled “Technical Documentation & Analysis: High Voltage Diamond Schottky Diodes”

This research demonstrates the critical influence of surface morphology on the performance of vertical Single Crystal Diamond (SCD) Schottky Barrier Diodes (SBDs) for high-power electronics.

  • High Voltage Performance: Vertical SCD SBDs achieved high blocking voltages (VBD) ranging from 2.4 kV to 2.6 kV across all tested surface morphologies (Smooth, Hillock-rich, Polished).
  • Record BFOM: The study achieved a Baliga Figure of Merit (BFOM) up to 21 MW/cm2 for VBD > 2 kV diamond SBDs, representing an approximate 7-fold increase over comparable literature devices.
  • Low On-Resistance: The lowest specific on-resistance (RonA) of 300 mΩ·cm2 was achieved on the polished SCD sample (S3), demonstrating the benefit of post-growth surface treatment.
  • Surface Morphology Impact: Smooth (Ra < 0.8 nm) and Polished (Ra 1.5 nm) surfaces yielded the best reverse characteristics, maintaining low leakage current density (JRev < 10-4 A/cm2) up to 2.2 kV.
  • Material Quality Requirement: Statistical analysis confirmed that low-defect density SCD substrates are essential for maximizing the feasible device area and achieving homogeneous, high-performance characteristics.
  • Fabrication Method: Devices were fabricated using MPCVD-grown, unintentionally doped (i-layer) SCD on highly Boron-Doped Diamond (BDD) HPHT substrates.

The following hard data points were extracted from the analysis of the high-voltage diamond Schottky diodes (Samples S1, S2, S3).

ParameterValueUnitContext
Maximum Blocking Voltage (VBD)2.4 - 2.6kVAchieved across all samples
Specific On-Resistance (RonA)300mΩ·cm2Lowest value (Polished Sample S3)
Reverse Current Density (JRev)< 10-4A/cm2Smooth (S2) and Polished (S3) up to 2.2 kV
Maximum Electric Field (EMax)1.6MV/cmHighest value (Smooth Sample S2)
Baliga Figure of Merit (BFOM)21MW/cm2Highest value (Polished Sample S3)
Net Doping Concentration (NA-ND)2.0 - 6.8 x 1014cm-3SCD i-layer (determined by C-V)
Ideality Factor (n)1.03-Smooth Sample S2 (Near ideal thermionic emission)
Schottky Barrier Height (ΊB)1.80eVHighest value (Polished Sample S3, determined by C-V)
RMS Surface Roughness (Ra)< 0.8nmSmooth Sample S2 (Measured by WLI)
Ohmic Contact Resistivity (ρ)1 x 10-5Ω·cm2TiP-tAu stack
i-layer Thickness17 to 28”mUnintentionally doped SCD
Substrate Doping (BDD)≈ 2 x 1020cm-3Highly Boron-Doped HPHT substrate

The vertical diamond Schottky diodes were fabricated using optimized MPCVD growth and multi-step post-processing techniques.

  1. Substrate Preparation:
    • Commercial 300 ”m thick, highly Boron-Doped (Type IIb) HPHT substrates were acid cleaned (3:1 Sulfuric/Nitric acid at 250 °C).
    • A H2-plasma etch (5 to 40 minutes) was conducted immediately before growth to minimize polishing damage influence.
  2. MPCVD Growth (i-layer):
    • System: Home-made Microwave Plasma-Enhanced Chemical Vapor Deposition (MWPECVD).
    • Gas Mixture: CH4/H2 ratio of 3% or 4%, with 0.15% O2/H2 added for quality control.
    • Pressure: 200 mbar.
    • Temperature: Substrate temperature stabilized at roughly 800 °C.
    • Result: Unintentionally doped SCD i-layers (17 ”m to 28 ”m thick) with NA < 1015 cm-3.
  3. Surface Polishing (Sample S3):
    • Mechanical polishing was performed to remove approximately 3 ”m of material and reduce RMS roughness to 1.5 nm.
    • A subsequent 10-minute, 2.2 kW H2 plasma etch at 800 °C was applied to mitigate subsurface polishing damage.
  4. Ohmic Contact Fabrication (Backside):
    • TiP-tAu stack deposited via electron-beam evaporation.
    • Rapid Thermal Annealing (RTA) performed in N2 atmosphere at 850 °C for 60 seconds, achieving 1 x 10-5 Ω·cm2 contact resistivity.
  5. Schottky Contact Fabrication (Frontside):
    • Short oxygen plasma ashing was used to enhance oxygen termination.
    • Schottky stack (Ti/Pt/Au) was deposited via electron-beam evaporation (Ti as Schottky metal, Pt as diffusion stop, Au as capping layer).

The successful fabrication of high-performance diamond SBDs relies on precise control over material quality, doping, thickness, and surface preparation—all core competencies of 6CCVD. We provide the necessary MPCVD diamond materials and processing services to replicate and advance this research.

To replicate the high-voltage vertical SBD structure, two primary 6CCVD materials are required:

  • Epitaxial Layer (i-layer): Optical Grade SCD
    • Requirement Match: The paper used unintentionally doped SCD (NA < 1015 cm-3) i-layers. Our Optical Grade SCD offers the highest purity and lowest defect density, crucial for achieving the high breakdown field (EMax ≈ 1.6 MV/cm) observed in the best performing samples (S2).
    • Thickness Control: We offer custom SCD thickness control from 0.1 ”m up to 500 ”m, easily accommodating the 17 ”m to 28 ”m layers used in this study.
  • Substrate Layer (p+): Heavy Boron Doped SCD (BDD)
    • Requirement Match: The paper utilized highly doped BDD substrates (NA ≈ 2 x 1020 cm-3) for the ohmic contact. 6CCVD specializes in Heavy Boron Doped SCD, capable of matching or exceeding this doping concentration for low-resistance vertical device architectures.
    • Substrate Dimensions: While the paper used 300 ”m thick substrates, 6CCVD can supply robust BDD substrates up to 10 mm thick, providing superior mechanical and thermal stability.

The research highlights that surface morphology and metalization stacks are critical performance differentiators. 6CCVD offers in-house services to optimize these parameters:

Research Requirement6CCVD CapabilityPerformance Advantage
Ultra-Smooth Surface (Ra < 0.8 nm)Precision Polishing (Ra < 1 nm)Guarantees the optimal surface morphology (like Sample S2) necessary to minimize leakage current (JRev < 10-4 A/cm2) and maximize EMax.
Custom Metalization Stack (Ti/Pt/Au)In-House Metalization ServicesWe offer deposition of Ti, Pt, and Au stacks, ensuring reliable, low-resistivity ohmic contacts (ρ = 1 x 10-5 Ω·cm2) and stable Schottky contacts, eliminating external processing variability.
Custom Device Dimensions (100-300 ”m diodes)Advanced Laser Cutting & ShapingWe provide custom laser cutting and shaping services for both SCD and PCD wafers up to 125 mm, allowing researchers to define precise diode diameters and geometries for statistical analysis and device scaling studies.
Low-Defect SubstratesHigh-Quality MPCVD GrowthOur stringent material quality control ensures low-defect SCD substrates, directly addressing the paper’s finding that high defect density limits feasible device area and increases reverse current density.

The performance of high-voltage diamond SBDs is highly sensitive to the interplay between crystal quality, surface termination, and processing steps (e.g., H2 plasma etching).

  • 6CCVD’s in-house PhD engineering team specializes in optimizing MPCVD growth recipes and post-processing techniques (polishing, etching) to precisely control surface morphology and defect density.
  • We offer expert consultation on material selection (SCD vs. BDD) and layer design (thickness and doping profiles) for high-voltage power electronics and similar Schottky Diode projects, ensuring optimal BFOM and breakdown characteristics.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

Vertical diamond Schottky diodes with blocking voltages VBD > 2.4 kV and ON-resistances RON <; 400 mΩcm2 were fabricated on homoepitaxially grown diamond layers with different surface morphologies. The morphology (smooth as-grown, hillock-rich, polished) influences the Schottky barrier, the carrier transport properties, and ultimately the device performance. The smooth as-grown sample exhibited a low reverse current density JRev <; 10-4 A/cm2 for reverse voltages up to 2.2 kV. The hillock-rich sample blocked similar voltages with a slight increase in the reverse current density (JRev <; 10-3 A/cm2). The calculated 1-D breakdown field, however, was reduced by 30%, indicating a field enhancement induced by the inhomogeneous surface. The polished sample demonstrated a similar breakdown voltage and reverse current density as the smooth as-grown sample, suggestingthat a polished surface can be suitable for device fabrication. However, statistical analysis of several diodes of each sample showed the importance of the substrate quality: a high density of defects both reduces the feasible device area and increases the reverse current density. In forward direction, the hillock-rich sample exhibited a secondary Schottky barrier, which could be fit with a modified thermionic emission (TEM) model employing the Lambert W-function. Both polished and smooth samples showed nearly ideal TEM with ideality factors 1.08 and 1.03, respectively. Compared with the literature, all three diodes exhibit an improved Baliga figure of merit for diamond Schottky diodes with VBD > 2 kV.

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