Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications

At a Glance

Metadata	Details
Publication Date	2017-02-20
Journal	Scientific Reports
Authors	Hiroshi Kawarada, Tetsuya Yamada, Dechen Xu, Hidetoshi Tsuboi, Y. Kitabayashi
Institutions	Waseda University
Citations	103
Analysis	Full AI Review Included

Technical Analysis and Commercial Documentation: Durability-Enhanced Diamond p-FETs

Reference: Kawarada, H. et al. Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications. Scientific Reports 7, 42368 (2017).

Executive Summary

This research establishes diamond as the only wide bandgap material capable of producing high-performance p-channel Field Effect Transistors (p-FETs) required for simplified complementary power inverter systems. The core achievements leverage 6CCVD’s expertise in specialized single crystal diamond (SCD) material preparation and interface engineering.

Record High Breakdown Voltage: Achieved a maximum breakdown voltage (V_B) of 1708 V in a C-H diamond MOSFET, a value comparable to state-of-the-art lateral SiC and GaN n-FETs.
Complementary Capability: Demonstrated high-voltage switching performance necessary for integration with existing n-channel SiC/GaN devices, simplifying gate drive circuitry for smart inverters.
Enhanced Durability & Stability: The two-dimensional hole gas (2DHG) channel exhibited stable operation across extreme temperatures, from 10 K (-263 °C) up to 400 °C (673 K).
Interface Engineering: Used high-temperature (450 °C) Atomic Layer Deposition (ALD) of Aluminum Oxide (Al₂O₃) to simultaneously act as the high-quality gate insulator, passivation layer, and the mechanism for 2DHG induction on the Hydrogen-terminated (C-H) diamond surface.
Performance Metrics: On-state drain current density (I_DS) reached 116 mA/mm, meeting required benchmarks for power device applications.
Material Requirements: Success hinges on precise homoepitaxial MPCVD growth of undoped diamond on heavily N-doped (001) substrates to manage charge compensation and field distribution.

Technical Specifications

The following table summarizes the hard data extracted from the high-voltage C-H diamond p-FET results.

Parameter	Value	Unit	Context
Maximum Breakdown Voltage (V_{B, Max})	1708	V	Achieved at L_GD=16 µm with 400 nm Al₂O₃ passivation layer.
V_B at High Temperature (200 °C)	1516	V	L_GD=17 µm. Demonstrates thermal stability.
V_B at Extreme Temperature (400 °C)	1200	V	Performance remains acceptable for power devices.
Maximum Drain Current Density (I_{DS, Max})	116	mA/mm	L_G=2 µm, L_GD=17 µm, 200 nm oxide.
Breakdown Field (V_B/L_GD)	1.0	MV/cm	Comparative performance to SiC and GaN.
Hole Channel Mobility (μ)	80	cm²V^-1s^-1	Estimated mobility at the Al₂O₃/C-H interface.
Negative Charge Density (N_s)	5 × 10¹²	cm^-2	Fixed negative charge inducing the 2DHG channel.
Gate Oxide Material	Al₂O₃	-	Deposited by Atomic Layer Deposition (ALD) at 450 °C.
Gate Oxide Thickness (t_ox)	200 / 400	nm	Used for gate insulator and passivation layer.
Diamond Epilayer Thickness	0.5	µm	Nominally undoped MPCVD layer.
Valence Band Offset (ΔE_V)	3.0-4.0	eV	Energy difference at the Al₂O₃/C-H diamond interface.

Comparative Performance (Diamond vs. Traditional WBG)

Wide Bandgap Planar FET	V_{B, Max} Breakdown Voltage	L_GD Gate Drain Distance	V_B/L_GD Breakdown Field	I_{DS, Max} Drain Current Density
SiC n-FET	1600 V	20 µm	0.8 MV/cm	90 mA/mm
AlGaN/GaN n-FET	1500 V	15 µm	1.0 MV/cm	300-600 mA/mm
C-H Diamond p-FET	1700 V	16 µm	1.0 MV/cm	110 mA/mm

Key Methodologies

The success of the high-voltage p-channel diamond MOSFET relies heavily on precise MPCVD growth parameters, interface cleaning, and high-temperature processing.

Substrate Selection and Growth:
- Substrate: Highly Nitrogen-doped (001) synthetic diamond (N concentration 10¹⁹ cm^-3) used to manage positive fixed charge compensation (N_B).
- Epilayer: A 0.5 µm nominally undoped diamond layer was grown homoepitaxially onto the substrate via Microwave Plasma-Assisted Chemical Vapor Deposition (MPCVD).
Surface Termination and Isolation:
- H-Termination: A critical remote plasma treatment (at 600 °C) was performed to ensure a clean, stable Hydrogen (C-H) termination across the surface, which is essential for 2DHG formation.
- Isolation: Local oxidation was used to replace H-terminations with O-terminations in non-channel areas, isolating the highly conductive C-H channel region.
Source/Drain Metalization:
- Titanium/Gold (Ti/Au) contacts were deposited. High-temperature processing induced the formation of stable Titanium Carbide (TiC) to ensure ohmic contact stability.
Gate Insulator and Passivation:
- Aluminum Oxide (Al₂O₃) was deposited using Atomic Layer Deposition (ALD) at a high temperature of 450 °C.
- ALD simultaneously created the gate insulator and the drift region passivation layer. Tested thicknesses were 200 nm and 400 nm. The 400 nm thickness resulted in the highest V_B (1708 V) due to better electric field management.
- The ALD Al₂O₃ film itself induced the 2DHG due to negative fixed charges near the C-H interface.

6CCVD Solutions & Capabilities

6CCVD is uniquely positioned to supply the high-quality SCD materials and specialized processing required to replicate or scale this breakthrough complementary power device technology. Our capabilities ensure engineers and researchers have access to the materials necessary for next-generation WBG electronics.

Applicable Materials

To replicate the high-voltage C-H diamond p-FET structure, 6CCVD recommends supplying the following custom MPCVD materials:

Substrates: Custom N-Doped (001) Single Crystal Diamond (SCD) Substrates. These must be highly doped (approaching 10¹⁹ cm^-3) to manage the internal electric field distribution for optimized breakdown voltage, as detailed in the simulation results (Fig. 6).
Epilayer Growth: High-Purity Undoped SCD Epitaxial Layers. We offer highly controlled, homoepitaxial MPCVD growth to achieve the required 0.5 µm thickness with ultra-low impurity levels, critical for maximizing hole mobility in the drift region.
Boron-Doped Diamond (BDD) Potential: While the core demonstration uses C-H 2DHG, the paper highlights BDD channels for high-temperature stability in MESFET/JFET structures. 6CCVD supplies Standard or Heavy Boron-Doped PCD/SCD for researchers exploring bulk p-channel controls or alternative high-temperature FET designs.

Customization Potential

The optimization of V_B and I_DS in this paper depended on precise dimensional control and specialized interfaces—all core strengths of 6CCVD’s manufacturing services.

Device Requirement in Paper	6CCVD Specific Service	Technical Advantage
Specific Thicknesses (0.5 µm epilayer, up to 500 µm total)	Custom Thickness SCD/PCD: We offer precise thickness control from 0.1 µm up to 500 µm for active layers, and substrates up to 10 mm.	Ensures repeatable control over device resistivity and capacitance.
High Surface Quality (for C-H termination)	Ultra-Smooth Polishing: Achieved Ra < 1 nm for SCD and Ra < 5 nm for PCD, essential for maximizing 2DHG uniformity and stability during ALD processing.	Minimizes interface defects (traps) that compromise V_B and hole mobility.
Custom Metalization Stack (Ti/Au Ohmic Contacts)	In-House Metalization Services: We offer deposition of Ti, Au, Pt, Pd, W, and Cu layers, enabling the replication of the required TiC/Au ohmic contacts for source/drain definition.	Provides a reliable, integrated starting wafer ready for customer-specific ALD/Gate patterning.
Custom Device Dimensions (L_G=2 µm, L_GD up to 22 µm)	Precision Laser Cutting and Dicing: We supply wafers and plates up to 125mm (PCD) cut precisely to match experimental requirements for optimal device layout definition.	Supports both research scale (small chips) and future mass production prototypes.

Engineering Support

6CCVD’s in-house team of PhD material scientists and technical engineers specialize in diamond interface physics and MPCVD growth recipes. We offer comprehensive consultation services to assist customers with:

Material Selection: Guiding researchers on the precise doping levels and growth conditions (HPHT vs. MPCVD) needed for charge compensation layers required for high-voltage complementary power FETs.
Interface Optimization: Consulting on pre-treatment protocols (e.g., C-H/O-termination strategies) to ensure maximum stability and reliability of the 2DHG channel interface.
Scaling Applications: Assisting in transitioning from lateral planar FETs (as demonstrated in this paper) to high-efficiency vertical power devices, such as diamond trench gate MOSFETs.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

Tech Support

Original Source

DOI: https://doi.org/10.1038/srep42368