Demonstration of qubit operations below a rigorous fault tolerance threshold with gate set tomography

At a Glance

Metadata	Details
Publication Date	2017-02-15
Journal	Nature Communications
Authors	Robin Blume-Kohout, John King Gamble, Erik Nielsen, Kenneth Rudinger, Jonathan Mizrahi
Institutions	Sandia National Laboratories
Citations	402
Analysis	Full AI Review Included

Technical Documentation & Analysis: MPCVD Diamond for Fault-Tolerant Quantum Computing

This document analyzes the research demonstrating single-qubit operations below the rigorous fault tolerance threshold using Gate Set Tomography (GST). The findings underscore the critical need for ultra-high-fidelity hardware platforms, a requirement perfectly addressed by 6CCVD’s specialized MPCVD diamond materials.

Executive Summary

Rigorous Fault Tolerance Achieved: The research successfully demonstrated single-qubit gate errors (G_I, G_X, G_Y) below the rigorous Fault Tolerance Quantum Error Correction (FTQEC) threshold of < 6.7 x 10^-4 (diamond norm).
Precision Characterization: Gate Set Tomography (GST) was utilized to achieve unprecedented precision, providing tight bounds on the diamond norm error, which is critical for bounding worst-case coherent errors.
Superior Error Metrics: GST proved superior to traditional Randomized Benchmarking (RB) by enabling direct computation of the diamond norm, confirming suitability for FT against general noise models.
Hardware Stability Critical: Iterative debugging guided by GST identified and mitigated non-Markovian noise, emphasizing the necessity of ultra-stable, low-decoherence hardware platforms, such as those built on high-purity diamond substrates.
Achieved Error Rates: Final diamond norm errors for the three gates ranged from 1.39 x 10^-4 to 1.62 x 10^-4 (95% confidence intervals), confirming the gates surpass the established FT threshold.
Scalability Implication: The methods used to achieve sub-threshold single-qubit gates generalize to two-qubit gates and multi-qubit systems, paving the way for scalable FTQEC architectures.

Technical Specifications

The following hard data points were extracted from the analysis of the trapped-ion qubit operations:

Parameter	Value	Unit	Context
FTQEC Diamond Norm Threshold	< 6.7 x 10^-4	Dimensionless	Rigorous threshold against general errors (Ref. 22)
Achieved Diamond Norm Error (G_X)	1.39 ± 0.22 x 10^-4	Dimensionless	95% Confidence Interval (CI)
Achieved Diamond Norm Error (G_Y)	1.62 ± 0.27 x 10^-4	Dimensionless	95% CI
Achieved Diamond Norm Error (G_I)	1.58 ± 0.15 x 10^-4	Dimensionless	95% CI
Maximum Gate Sequence Length (L)	8,192	Gates	Used for GST error amplification
Qubit Frequency Separation	12.6428	MHz	Hyperfine clock states of ¹⁷¹Yb⁺
HOA-2 Trap Axial Frequency	0.5	MHz	Ion trapping stability
HOA-2 Trap Radial Frequencies	2.2 and 2.8	MHz	Ion trapping stability
Required Precision for Unitarity Benchmarking	10^-8	Dimensionless	Required to bound diamond norm using RB-like methods (GST achieved this efficiently)

Key Methodologies

The experiment relied on Gate Set Tomography (GST) to systematically characterize and improve the quantum logic operations on a single trapped ¹⁷¹Yb⁺ ion.

Qubit Platform: A single ¹⁷¹Yb⁺ ion was trapped in a linear surface electrode ion trap (Sandia HOA-2 trap).
Gate Implementation: Logic gates (G_I, G_X, G_Y) were realized using a microwave horn applying broadband composite pulses (BB1) near-resonant with the qubit levels (12.6428 MHz).
GST Sequence Design: GST utilized periodic sequences based on short ‘germs’ (11 germs used) repeated many times (up to L=8,192) and sandwiched between six fiducial sequences. This design collectively amplifies every physical parameter in the gate set.
Iterative Improvement: The GST analysis guided iterative hardware and pulse sequence improvements over five experimental runs (e.g., stabilizing microwave amplifier temperature, active drift control of qubit frequency, and upgrading the G_I dynamical decoupling sequence).
Error Quantification: The diamond norm error, ||G - G_ideal||_◊, was computed using a semidefinite program, providing a rigorous, gauge-optimized metric for worst-case error rates.
Non-Markovianity Analysis: The log-likelihood score (N_σ) was used to quantify the violation of the Markovian model, allowing researchers to debug and reduce time-dependent noise sources (drift).

6CCVD Solutions & Capabilities

The achievement of fault-tolerant thresholds in quantum computing is fundamentally limited by physical hardware stability, surface quality, and thermal management. 6CCVD’s MPCVD diamond materials are engineered to meet the extreme demands of next-generation quantum platforms, including trapped-ion surface electrode traps.

Applicable Materials

Research Requirement	6CCVD Material Recommendation	Rationale and Capability Match
Ultra-Low Decoherence Substrate (Minimizing surface charge noise/ion heating)	Optical Grade Single Crystal Diamond (SCD)	SCD offers the highest purity and lowest defect density, minimizing stray electric fields and surface noise that contribute to non-Markovian errors and ion heating. Polishing to Ra < 1nm ensures an atomically smooth surface.
High Thermal Stability & Dissipation (Managing heat from control electronics)	High Thermal Conductivity SCD/PCD Substrates	Diamond’s exceptional thermal conductivity is vital for dissipating heat generated by microwave control lines and integrated electronics, ensuring the temperature stability required for high-fidelity, long-sequence GST experiments. Substrates available up to 10mm thick.
Scalable Trap Fabrication (Moving beyond single-qubit systems)	Large Area Polycrystalline Diamond (PCD)	We provide custom PCD plates/wafers up to 125mm in diameter, enabling the fabrication of complex, scalable surface electrode arrays necessary for multi-qubit FTQEC architectures. PCD can be polished to Ra < 5nm (inch-size).
Integrated Control Elements (Future integration of photonics/NV centers)	Boron-Doped Diamond (BDD)	BDD offers tunable conductivity for integrated microelectronics, waveguides, and high-Q resonators directly on the quantum substrate, supporting advanced quantum control schemes.

Customization Potential

The development of high-fidelity ion traps requires precise material engineering and integration capabilities that 6CCVD provides:

Custom Dimensions: We supply SCD and PCD wafers in custom dimensions and thicknesses (SCD/PCD from 0.1µm to 500µm) tailored to specific trap geometries (e.g., linear surface electrode traps).
Advanced Metalization: The fabrication of surface electrodes requires high-quality metal stacks. 6CCVD offers internal metalization services, including common stacks like Ti/Pt/Au, Pd, W, and Cu, ensuring robust, low-resistance control lines directly on the diamond substrate.
Precision Processing: Our capabilities include precision laser cutting and shaping services to meet the exact dimensional tolerances required for mounting and integration into cryogenic or vacuum systems.

Engineering Support

The iterative debugging process highlighted in the research—moving from non-Markovian to highly stable operations—is heavily dependent on material quality. 6CCVD’s in-house PhD team specializes in material science for quantum applications.

We offer expert consultation to assist researchers and engineers in selecting the optimal diamond grade (SCD vs. PCD), surface preparation (polishing), and metalization scheme necessary to minimize decoherence and maximize thermal stability for similar Trapped-Ion Quantum Computing projects.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

Tech Support

Original Source

DOI: https://doi.org/10.1038/ncomms14485