Direct Integration of Polycrystalline Diamond With 3C‐SiC for Enhanced Thermal Management in GaN HEMTs - Impact of Grain Structure and Interface Engineering
At a Glance
Section titled “At a Glance”| Metadata | Details |
|---|---|
| Publication Date | 2025-07-10 |
| Journal | Advanced Materials Technologies |
| Authors | Chiharu Moriyama, Zhe Cheng, Zifeng Huang, Yutaka Ohno, Koji Inoue |
| Institutions | Peking University, Tohoku University |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: Direct Integration of MPCVD Diamond for GaN HEMTs
Section titled “Technical Documentation & Analysis: Direct Integration of MPCVD Diamond for GaN HEMTs”Executive Summary
Section titled “Executive Summary”This research successfully demonstrates the direct integration of Polycrystalline Diamond (PCD) with 3C-SiC for advanced thermal management in GaN High-Electron-Mobility Transistors (HEMTs), achieving a critical milestone in high-power electronics scaling.
- Scale and Stability: Successful, crack-free direct bonding of 3C-SiC/GaN layers onto 2-inch MPCVD PCD wafers was achieved using Surface-Activated Bonding (SAB) at room temperature, demonstrating scalability for industrial applications.
- Interface Engineering: High-temperature annealing (1100 °C) transformed the initial 7 nm amorphous bonding layer into a stable 13 nm polycrystalline SiC layer, crucial for robust thermal and structural integrity.
- Superior Thermal Properties: The PCD growth surface exhibited high thermal conductivity (2088 W/mK), surpassing the Single Crystal Diamond (SCD) reference (1971 W/mK).
- Enhanced Interface Conductance: The Thermal Boundary Conductance (TBC) at the 3C-SiC/PCD interface (92 MW/m2K) was significantly higher than the 3C-SiC/SCD interface (55 MW/m2K).
- Thermal Bottleneck Identified: The overall thermal resistance (RTH) of the GaN HEMT on PCD was 27% higher than on SCD due to the fine-grained nucleation layer (average grain size 2.2 µm) acting as a thermal bottleneck via increased phonon scattering.
- Key Recommendation: Removing the fine-grained nucleation layer via mechanical polishing is essential to fully leverage PCD’s intrinsic thermal advantages for next-generation high-power devices.
Technical Specifications
Section titled “Technical Specifications”| Parameter | Value | Unit | Context |
|---|---|---|---|
| PCD Wafer Size Demonstrated | 2 | inch | Successful scale-up for GaN HEMT integration |
| PCD Wafer Thickness | 400 | µm | Substrate thickness used for bonding |
| PCD Growth Surface Thermal Conductivity (k) | 2088 | W/mK | Measured via TDTR; higher than SCD reference |
| SCD Thermal Conductivity (k) | 1971 | W/mK | Measured via TDTR |
| PCD Growth Surface Roughness (Ra) | 2.48 | nm | Roughness of the surface successfully bonded |
| Highly Polished PCD Ra (Reference) | 0.1 | nm | Achieved on areas without grain boundaries |
| 3C-SiC/PCD TBC (Thermal Boundary Conductance) | 92 | MW/m2K | Post-annealing interface performance |
| 3C-SiC/SCD TBC (Thermal Boundary Conductance) | 55 | MW/m2K | Reference interface performance |
| Amorphous Interface Layer Thickness (Pre-anneal) | ~7 | nm | Formed during room temperature SAB process |
| Polycrystalline SiC Layer Thickness (Post-anneal) | ~13 | nm | Formed after 1100 °C annealing |
| RTH (HEMT w/o Gate) on PCD | 3.3 | K-mm/W | Thermal resistance (lower is better) |
| RTH (HEMT w/o Gate) on SCD | 2.6 | K-mm/W | Thermal resistance (27% lower than PCD) |
| Average Grain Diameter (PCD Growth Surface) | 55.9 | µm | Coarse-grained structure, high k |
| Average Grain Diameter (PCD Nucleation Surface) | 2.2 | µm | Fine-grained structure, thermal bottleneck |
Key Methodologies
Section titled “Key Methodologies”The integration and characterization relied on precise MPCVD growth and advanced bonding/analysis techniques:
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PCD Substrate Synthesis:
- Method: Microwave Plasma Chemical Vapor Deposition (MPCVD).
- Substrate Preparation: Si substrates mechanically pre-treated with 50-100 nm diamond powder for nucleation sites.
- Gas Mixture: Methane (2-5% volume fraction) in Hydrogen.
- Power/Pressure: 5.6 KW microwave power, 200 Torr working pressure.
- Temperature Control: Substrate temperature optimized between 700-1100 °C via Z-axis height adjustment.
- Deposition Time: 400 hours maintained for uniform diamond layer formation.
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Surface Preparation and Bonding:
- PCD Post-Growth: PCD separated from Si substrate; growth surface mechanically polished and cleaned (sulfuric acid-hydrogen peroxide mixture).
- Bonding Technique: Surface-Activated Bonding (SAB) performed at room temperature.
- Activation: Simultaneous irradiation of diamond and 3C-SiC surfaces by Argon Fast Atom Beam (Ar FAB).
- FAB Parameters: 1.6 kV voltage, 160 mA current, 1.0 x 10-7 Pa high vacuum.
- Contact: Surfaces brought into contact under 1 GPa load for 180 s.
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Post-Bonding Processing and Characterization:
- Annealing: Thermal stability assessed via annealing at 1100 °C for 10 minutes (resulting in 13 nm polycrystalline SiC interface).
- Thermal Measurement: Time-Domain Thermoreflectance (TDTR) used to measure thermal conductivity (k) and Thermal Boundary Conductance (TBC).
- Interface Analysis: Transmission Electron Microscopy (TEM) and Energy-Dispersive X-ray Spectroscopy (EDS) used to analyze the 3C-SiC/PCD interface structure and elemental distribution.
- Surface/Grain Analysis: Atomic Force Microscopy (AFM) measured surface roughness (Ra); Electron Backscatter Diffraction (EBSD) analyzed crystal orientation and grain size distribution (2.2 µm nucleation vs. 55.9 µm growth).
6CCVD Solutions & Capabilities
Section titled “6CCVD Solutions & Capabilities”This research validates the critical role of high-quality MPCVD diamond substrates in achieving next-generation thermal management for GaN HEMTs. 6CCVD is uniquely positioned to supply the materials and processing required to replicate, optimize, and scale this technology.
Applicable Materials for Replication and Optimization
Section titled “Applicable Materials for Replication and Optimization”The study highlights the need for both high-quality PCD for cost-effective scaling and SCD for baseline performance comparison.
| Material Requirement | 6CCVD Solution | Technical Advantage |
|---|---|---|
| High-k PCD Substrates | Thermal Grade PCD (Polycrystalline Diamond) | We offer custom PCD plates/wafers up to 125mm in diameter, exceeding the 2-inch scale demonstrated here, enabling true industrial scalability. |
| High-k SCD Substrates | Electronic Grade SCD (Single Crystal Diamond) | Available in thicknesses from 0.1µm to 500µm. Essential for establishing the thermal baseline (RTH = 2.6 K-mm/W) and optimizing interface TBC. |
| Future Electrical Integration | Boron-Doped Diamond (BDD) | While not used in this study, BDD is available for future research requiring electrically conductive diamond layers for advanced device architectures or ohmic contacts. |
Customization Potential for Interface Engineering
Section titled “Customization Potential for Interface Engineering”The paper identifies the fine-grained nucleation layer as the primary thermal bottleneck, recommending its removal via mechanical polishing to enhance heat dissipation. 6CCVD specializes in the precise material engineering required to overcome this challenge.
- Large-Area Polishing: 6CCVD offers advanced polishing services for PCD wafers up to inch-size, achieving roughness values (Ra < 5 nm). We can execute the critical step of removing the fine-grained nucleation layer (up to ~100 µm thick) to maximize thermal transport efficiency, as recommended by the researchers.
- Ultra-Smooth SCD Polishing: For the highest thermal performance benchmarks, our SCD polishing achieves Ra < 1 nm, ensuring optimal surface quality for advanced bonding techniques like SAB.
- Custom Dimensions and Thickness: We provide custom plates and wafers up to 125mm (PCD) and substrates up to 10mm thick, allowing researchers to test various thermal spreading geometries (e.g., shorter LG, wider WG) referenced in the study.
- Metalization Services: The HEMT fabrication required Ti/Al/Ti/Au and Ni/Au metalization for ohmic and Schottky contacts. 6CCVD offers internal metalization capabilities (Au, Pt, Pd, Ti, W, Cu) to support full device fabrication workflows.
Engineering Support
Section titled “Engineering Support”6CCVD’s in-house PhD team specializes in MPCVD diamond growth and characterization (including thermal properties and grain structure analysis, mirroring the EBSD and TDTR techniques used in this paper). We can assist clients with:
- Material Selection: Consulting on the optimal PCD grain size distribution and SCD quality necessary to minimize phonon scattering and maximize thermal conductivity (k).
- TBC Optimization: Providing materials with tailored surface preparation to achieve high TBC values (e.g., exceeding the 92 MW/m2K demonstrated here).
- Global Logistics: Offering reliable global shipping (DDU default, DDP available) to ensure prompt delivery of high-value diamond substrates worldwide.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
Abstract The direct integration of polycrystalline diamond (PCD) with semiconductors is crucial for enhancing heat dissipation in high‐power electronics. However, achieving low surface roughness (<1 nm) remains challenging. In this study, the direct bonding of PCD to 3C‐SiC for GaN high‐electron‐mobility transistors (HEMTs) on a 2‐inch PCD wafer is demonstrated using an advanced bonding technique. The PCD wafer (surface roughness: 2.48 nm) is bonded at room temperature, forming a 7 nm‐thick amorphous layer, which transformed into a 13 nm‐thick polycrystalline SiC layer after annealing at 1100 °C without cracks or separations. Thermal analysis revealed higher thermal conductivity of PCD’s growth surface than single‐crystal diamond (SCD). However, the thermal resistance ( R TH ) of GaN HEMTs on PCD is 27% higher than on SCD, attributed to phonon scattering from smaller grain sizes on the nucleation surface. Removing the fine‐grained nucleation layer can enhance heat dissipation. This successful direct bonding of PCD with 3C‐SiC overcomes key integration challenges, enabling improved thermal transport and high‐power device reliability. To fully utilize PCD’s thermal advantages, grain size optimization and interface engineering are essential to reduce phonon scattering, improve thermal transport efficiency, and maximize device performance for next‐generation high‐power electronics.