Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications

At a Glance

Metadata	Details
Publication Date	2025-03-27
Journal	ACS Applied Electronic Materials
Authors	Xiaoyang Ji, Sai Charan Vanjari, Daniel Francis, Jerome A. Cuenca, Arpit Nandi
Institutions	Cardiff University, University of Bristol
Citations	1
Analysis	Full AI Review Included

6CCVD Technical Documentation: Interface Engineering for GaN-on-Diamond Thermal Management

Reference Paper: Thermal Boundary Resistance Reduction by Interfacial Nanopatterning for GaN-on-Diamond Electronics Applications (ACS Appl. Electron. Mater. 2025, 7, 2939-2946)

Executive Summary

This research validates advanced interface engineering techniques using MPCVD diamond to significantly mitigate the critical thermal bottleneck in high-power GaN High Electron Mobility Transistors (HEMTs).

Core Achievement: Demonstrated a 2.6x reduction in the effective Thermal Boundary Resistance (TBR_eff) at the GaN/Diamond interface.
TBR_eff Improvement: TBR_eff was successfully lowered from 101 m²·K/GW (planar interface) to 39 m²·K/GW using nanoscale patterning.
Methodology: The reduction was achieved by combining high-temperature annealing (800 °C to 1000 °C) of a SiN_x dielectric interlayer with nanoscale trench patterning (200 nm pitch) in the GaN layer prior to diamond deposition.
Material Densification: Annealing increased the thermal conductivity of the SiN_x interlayer by a factor of 2, crucial for efficient phonon transmission.
Interface Mechanism: The nanopatterning strategy increased the nominal contact area between the GaN and the MPCVD diamond, overcoming limitations caused by weak adhesion and carbide bond formation in planar interfaces.
Application Relevance: This work provides a scalable, thermally and mechanically robust solution for integrating MPCVD diamond substrates, paving the way for next-generation ultrahigh power density GaN-on-Diamond devices.

Technical Specifications

The following hard data points were extracted from the experimental results concerning interface optimization and thermal performance:

Parameter	Value	Unit	Context
TBR_eff Reduction Factor	2.6x	N/A	Achieved via 200 nm pitch nanopatterning.
Planar TBR_eff (Reference)	101	m²·K/GW	Unpatterned GaN/Diamond interface.
Patterned TBR_eff (Minimum)	39	m²·K/GW	200 nm pitch width, 300 nm trench depth.
SiN_x Interlayer Thickness	8, 13, 22	nm	Tested thicknesses showing linear TBR_eff dependence at 800 °C.
SiN_x Annealing Temperature (Optimal)	800	°C	Yielded lowest SiN_x TBR_eff (5 m²·K/GW for 8 nm film).
Diamond Film Thickness	1	µm	Deposited via MPCVD for thermal measurement.
Diamond Deposition Temperature	~700	°C	Substrate temperature during MPCVD growth.
SiN_x Thermal Conductivity (Annealed)	~1.2	W/m·K	Average value after 800 °C annealing.
Trench Pitch Widths Tested	800 to 200	nm	Inverse correlation observed between pitch and TBR_eff.
Maximum Principal Stress (GaN)	368 - 387	MPa	Simulated stress in GaN corners, well below tensile strength (4-7 GPa).

Key Methodologies

The experiment relied on precise thin-film deposition, nanoscale patterning, and controlled MPCVD diamond growth, all areas where 6CCVD provides expert support and materials.

Interlayer Deposition and Densification: SiN_x thin films (25 nm or 50 nm) were deposited via PECVD onto GaN/Diamond wafers. Rapid Thermal Annealing (RTA) was performed at 600 °C, 800 °C, and 1000 °C for 10 minutes under N₂ to densify the dielectric layer and improve thermal conductivity.
Nanopatterning of GaN: E-beam lithography defined trench patterns (100 nm width, 200-800 nm pitch) in a PMMA mask. Reactive Ion Etching (RIE) using SF₆ plasma transferred the pattern to the SiN_x hard mask, followed by RIE using Cl₂/Ar plasma to etch the underlying GaN layer (target depth 300 nm).
Conformal SiN_x Recoating: A second, thin (10 nm) PECVD SiN_x layer was conformally deposited over the patterned GaN trenches and annealed at 1000 °C.
Diamond Nucleation: Samples were immersed in a nano-diamond colloid solution (positive zeta-potential) under ultrasonic agitation to seed the surface.
MPCVD Diamond Growth: A 1 µm diamond film was deposited using a custom MPCVD system at 5 kW power, 160 mbar, and 3% CH₄/H₂ gas flow, maintaining the substrate temperature at approximately 700 °C.
Thermal Characterization: Nanosecond Transient Thermoreflectance (ns-TTR) was used to measure the TBR_eff. A Cr (10 nm) adhesion layer and an Au (160 nm) transducer layer were thermally evaporated onto the diamond surface prior to measurement.

6CCVD Solutions & Capabilities

6CCVD is uniquely positioned to supply the high-quality MPCVD diamond materials and advanced interface engineering required to replicate and extend this critical GaN-on-Diamond research.

Applicable Materials

To achieve the record-high thermal performance demonstrated in this study, researchers require diamond materials optimized for thermal management and interface adhesion.

Research Requirement	6CCVD Material Solution	Key Capability Match
High Thermal Conductivity Substrate	Thermal Grade Polycrystalline Diamond (PCD)	PCD wafers up to 125mm diameter, ideal for high-power GaN HEMT heat spreading.
Thin Film Deposition	PCD Films (0.1 µm - 500 µm)	Custom thickness control to replicate the 1 µm diamond layer used, or to provide thicker films for enhanced heat spreading.
Interface Adhesion Layer	Boron-Doped Diamond (BDD)	BDD films can be used as an alternative interlayer or nucleation layer to promote robust carbide bond formation, potentially reducing the need for complex SiN_x densification steps.
Transducer Layer	Optical Grade Single Crystal Diamond (SCD)	SCD films (Ra < 1nm) are available for applications requiring ultra-low surface roughness for subsequent thin-film deposition or advanced optical characterization.

Customization Potential for Interface Engineering

The success of this research hinges on precise control over dimensions, patterning, and metalization—all standard services offered by 6CCVD.

Custom Dimensions: The study utilized patterned interfaces on GaN/Diamond wafers. 6CCVD supplies custom PCD plates and wafers up to 125mm, ready for advanced lithography and RIE processing.
Thickness Control: We offer precise control over diamond thickness, from 0.1 µm films (for interface studies) up to 10 mm substrates, ensuring optimal thermal resistance matching for specific device architectures.
Metalization Services: The ns-TTR measurement required a Cr/Au transducer stack. 6CCVD provides in-house metalization capabilities, including the deposition of Au, Pt, Pd, Ti, W, and Cu films, allowing researchers to receive pre-metalized diamond substrates ready for immediate testing.
Substrate Preparation: We offer advanced polishing (Ra < 5nm for inch-size PCD) and laser cutting services to prepare substrates for complex patterning techniques like the trenches used in this study.

Engineering Support

The optimization of the GaN/SiN_x/Diamond interface involves complex trade-offs between thermal performance, mechanical stress, and MPCVD growth parameters (e.g., managing voids in trenches).

6CCVD’s in-house PhD material science team specializes in MPCVD recipe optimization and heterogeneous interface design. We offer consultation services to assist engineers and scientists in selecting the optimal diamond material, interlayer strategy, and processing parameters needed to replicate or extend this TBR reduction methodology for specific GaN-on-Diamond HEMT projects.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

GaN high electron mobility transistors (HEMTs) on SiC substrates are the highest performing commercially available transistors for high-power, high-frequency applications. However, Joule self-heating limits the maximum areal power density, i.e., operating power is derated to ensure the lifetime of GaN-based devices. Diamond is attractive as a heat sink due to its record-high thermal conductivity combined with its high electrical resistivity. GaN-on-diamond devices have been demonstrated, bringing the diamond as close as possible to the active device area. The GaN/diamond interface, close to the channel heat source, needs to efficiently conduct high heat fluxes, but it can present a significant thermal boundary resistance (TBR). In this work, we implement nanoscale trenches between GaN and diamond to explore new strategies for reducing the effective GaN/diamond TBR (TBReff). A 3× reduction in GaN/diamond TBReff was achieved using this approach, which is consistent with the increased contact area; thermal properties were measured using nanosecond transient thermoreflectance (ns-TTR). In addition, the SiN x dielectric interlayer between the GaN and diamond increased its thermal conductivity by 2× through annealing, further reducing the TBR. This work demonstrates that the thermal resistance of heterogeneous interfaces can be optimized by nanostructured patterning and high-temperature annealing, which paves the way for enhanced thermal management in future device applications.

Tech Support

Original Source

DOI: https://doi.org/10.1021/acsaelm.5c00119