Over 50 mA Current in Interdigitated Diamond Field Effect Transistor
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2024-09-03 |
| Journal | IEEE Electron Device Letters |
| Authors | Damien Michez, Juliette Letellier, Imane Hammas, Julien Pernot, Nicolas Rouger |
| Institutions | Laboratoire Plasma et Conversion dâEnergie, UniversitĂ© Grenoble Alpes |
| Citations | 4 |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: High Current Diamond JFET
Section titled âTechnical Documentation & Analysis: High Current Diamond JFETâThis document analyzes the research paper âOver 50 mA current in interdigitated diamond field effect transistorâ to provide technical specifications and align the findings with 6CCVDâs advanced MPCVD diamond material and fabrication capabilities.
Executive Summary
Section titled âExecutive SummaryâThis research successfully demonstrates the highest current value reported for a bulk diamond Field Effect Transistor (FET) by employing an interdigitated architecture and leveraging homogeneous, large-area CVD diamond growth.
- Record Performance: Achieved a total current exceeding 50 mA (3.5 mA/mm) at VDS = -15 V, VGS = 0 V, and 450 K, confirming diamondâs potential for high-power electronics.
- Architecture: The device utilized an interdigitated Junction FET (JFET) design featuring 24 parallel fingers, resulting in a large total gate width of 14.7 mm.
- Material Stack: The device relies on high-quality, multi-layer MPCVD diamond: a heavily boron-doped (p++) ohmic contact layer (3.6 mΩ·cm) grown selectively over a p-doped channel layer (1.52 Ω·cm) on an n-type HPHT substrate.
- Limiting Factor Identified: At high operating temperatures (450 K), the device performance is limited not by the conduction channel resistance, but by the device access resistance (RA), specifically the p++ layer bottleneck.
- Specific Resistance: The device demonstrated a specific ON-resistance (RON·S) of 600 mΩ·cm2 at 450 K.
- Methodology: Fabrication involved MPCVD growth, Reactive Ion Etching (RIE) for mesa structuring, selective growth of the p++ layer, and Ti/Pt/Au tri-metalization followed by 600 °C annealing.
- Conclusion: The study validates that diamond is a sufficiently mature material for fabricating complex, interdigitated devices required for next-generation power electronics.
Technical Specifications
Section titled âTechnical SpecificationsâThe following hard data points were extracted from the characterization of the interdigitated diamond JFET:
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Peak Total Current (IDS) | > 50 | mA | VDS = -15 V, VGS = 0 V, 450 K |
| Specific ON-Resistance (RON·S) | 600 | mΩ·cm2 | At 450 K |
| Threshold Voltage (Vth) | 50 | V | Measured at 450 K |
| Total Gate Width (WG) | 14.7 | mm | 24 parallel fingers |
| Channel Layer Resistivity (p-type) | 1.52 | Ω·cm | Extracted via TLM at 450 K (Target B: 2.1017 cm-3) |
| Access Layer Resistivity (p++-type) | 3.6 | mΩ·cm | Extracted via TLM at 450 K (Target B: > 3.1020 cm-3) |
| Channel Layer Thickness | 350 | nm | MPCVD p-doped layer |
| Access Layer Thickness | 280 | nm | Selective MPCVD p++ layer |
| Substrate Doping (n-type) | â 1019 | cm-3 | HPHT (100) |
| Metalization Stack | Ti/Pt/Au (30/40/50) | nm | Ohmic contact, 600 °C annealed |
| Operating Temperature | 450 | K | Highest current reported for bulk diamond FET |
Key Methodologies
Section titled âKey MethodologiesâThe interdigitated JFET fabrication process relied heavily on precise MPCVD growth and advanced post-processing techniques:
- Substrate Preparation: Used a (100) HPHT n-doped diamond substrate (Nitrogen concentration â 1019 cm-3, thickness â 500 ”m).
- Channel Layer Growth: MPCVD was used to grow the p-doped channel layer (target Boron concentration = 2.1017 cm-3, thickness = 350 nm).
- Mesa Structuring: The p-layer was etched using Reactive Ion Etching (RIE) with O2/CF4 plasma to confine the current and electrically insulate the device fingers.
- Ohmic Layer Selective Growth: A heavily boron-doped (p++) diamond layer (target Boron concentration > 3.1020 cm-3, thickness = 280 nm) was grown selectively via MPCVD to form low-resistance access regions.
- Metal Contact Deposition: A Ti/Pt/Au (30/40/50 nm) tri-metal multilayer was deposited by evaporation for drain, source, and gate contacts.
- Annealing: The metal stack was annealed at 600 °C for one hour to promote TiC bonding and reduce contact resistance.
- Surface Termination: An ozone plasma treatment (172 nm UV lamp, 500 mbar O2 pressure) was performed to achieve oxygen termination and eliminate surface currents.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & Capabilitiesâ6CCVD is uniquely positioned to supply the high-quality, custom MPCVD diamond materials and fabrication services necessary to replicate this high-performance JFET or advance the research toward commercial power electronics applications.
Applicable Materials for Replication and Advancement
Section titled âApplicable Materials for Replication and AdvancementâThe core challenge identified in the paper is optimizing the p++ access layer to reduce resistance. 6CCVD specializes in the precise control of Boron Doping Density (BDD) required for these critical layers.
| Component Requirement | 6CCVD Material Solution | Customization Focus |
|---|---|---|
| p++ Ohmic Contact Layer | Heavy Boron Doped PCD or SCD (BDD) | Ultra-high doping (> 3.1020 cm-3) for minimal access resistance (RA). We offer precise control over BDD to optimize the bottleneck region (R1). |
| p-type Channel Layer | Epitaxial BDD Layers (SCD/PCD) | Homogeneous, low-defect density layers (target B: 2.1017 cm-3) up to 500 ”m thick, ensuring consistent channel resistivity (R6). |
| Substrate/Template | High-Quality SCD or PCD Wafers | Available in (100) orientation, up to 125 mm diameter (PCD), providing the large, homogeneous area required for scaling interdigitated structures. |
Customization Potential for Power Electronics Engineers
Section titled âCustomization Potential for Power Electronics Engineersâ6CCVDâs in-house capabilities directly address the complex fabrication steps utilized in this JFET research:
- Large Area Homogeneity: The paper emphasizes the need for homogeneous, large-size diamond layers. 6CCVD provides PCD wafers up to 125 mm in diameter, enabling the fabrication of interdigitated devices with total gate widths significantly larger than the 14.7 mm demonstrated here.
- Precise Thickness Control: We offer SCD and PCD layers with thicknesses ranging from 0.1 ”m to 500 ”m, allowing researchers to fine-tune the 350 nm channel and 280 nm access layers for optimal performance and breakdown voltage.
- Advanced Metalization Services: The device relies on a critical Ti/Pt/Au tri-metal stack for ohmic contact formation. 6CCVD offers internal metalization services including Au, Pt, Pd, Ti, W, and Cu, ensuring high-quality, low-resistance contacts tailored to specific annealing requirements (e.g., 600 °C).
- Custom Shaping and Structuring: While the paper used RIE for mesa structuring, 6CCVD offers precision laser cutting and shaping services for rapid prototyping and defining complex interdigitated geometries on wafers up to 10 mm thick.
Engineering Support
Section titled âEngineering Supportâ6CCVDâs in-house PhD team specializes in the material science of wide bandgap semiconductors. We offer expert consultation to assist engineers and scientists in:
- Material Selection: Optimizing the doping profiles and layer thicknesses (p/p++) to minimize the access resistance (RA), which the paper identified as the current limiting factor at high temperatures.
- Interface Engineering: Advising on surface termination and metalization schemes to achieve stable, low-resistance ohmic contacts required for high-current Diamond JFET and MOSFET projects.
- Scaling: Providing material solutions for scaling up interdigitated architectures to achieve total currents far exceeding 50 mA for industrial power converter applications.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
This letter presents the bulk diamond field-effect transistor (FET) with the\nhighest current value reported at this moment. The goal was to drastically\nincrease the current of this type of device by increasing the total gate width\nthanks to an interdigitated architecture and homogeneous growth properties. We\nreport the results obtained by fabricating and characterizing an interdigitated\njunction FET (JFET). The device develops a total gate width of 14.7 mm, with 24\nparalleled fingers and a current higher than 50 mA at VDS = -15 V, VGS = 0 V,\nat 450 K and under illumination which is the highest value reported for a bulk\ndiamond FET. Its specific ON-resistance and threshold voltage are respectively\n608 m$\Omega$.cm${}^2$, 50 V. From Transfer length method (TLM) measurements we\nextract a resistivity of 3.6 m$\Omega$.cm for a heavily boron-doped\n(p++)-diamond layer and 1.52 $\Omega$.cm for a 2.1017 cm-3 p-doped diamond\nlayer at 450 K. We measured the drain current versus gate voltage\ncharacteristics at high temperature showing that it is no longer the conduction\nchannel resistance but the device access resistance that is predominant. This\nstudy indicates that it is possible to drastically improve the ON-state of FETs\nby using an interdigitated architecture, while using homogeneous large size\ndiamond layers grown by CVD.\n