H-Terminated Diamond MOSFETs on High-Quality Diamond Film Grown by MPCVD

At a Glance

Metadata	Details
Publication Date	2023-08-08
Journal	Crystals
Authors	Wenxiao Hu, Xinxin Yu, Tao Tao, Kai Chen, Yucong Ye
Institutions	Nanjing University, Institute of Electronics
Citations	4
Analysis	Full AI Review Included

Technical Analysis and Documentation: High-Performance H-Terminated Diamond MOSFETs

Executive Summary

This documentation analyzes the successful fabrication of high-performance H-terminated diamond MOSFETs utilizing high-quality, atomically flat single-crystal diamond (SCD) grown by Microwave Plasma Chemical Vapor Deposition (MPCVD).

Material Achievement: High-quality SCD epitaxial layers were grown at a high rate (~7 µm/h) without intentional nitrogen doping, ensuring high material purity (confirmed by PL analysis).
Surface Engineering: A critical pre-etching process was employed to remove surface defects and polishing damage, resulting in an atomically flat surface.
Roughness Reduction: The root mean square (RMS) roughness was dramatically reduced from 0.92 nm (polished substrate) down to 0.18 nm (thick epitaxial layer) in a 5 µm x 5 µm area.
Crystal Quality Improvement: Epitaxy enhanced crystal quality, evidenced by a reduction in the X-ray Diffraction (400) rocking curve Full Width at Half Maximum (FWHM) from 0.017° to 0.015°.
Device Performance: MOSFET performance was significantly enhanced on the epitaxial layer, achieving a 54% improvement in saturated current density (up to 200 mA/mm).
Reduced Defects: On-resistance (R_on) was lowered to 95 Ω·mm, and transfer curve hysteresis was significantly reduced, confirming the effectiveness of the low-defect epitaxial layer in minimizing carrier trapping.

Technical Specifications

The following hard data points were extracted from the research paper detailing the material properties and device performance metrics.

Parameter	Value	Unit	Context
Epitaxial Growth Rate	~7	µm/h	Achieved without nitrogen doping
Epitaxial Layer Thickness	~7	µm	Thickest layer (Sample 3)
Initial Substrate RMS Roughness	0.92	nm	Polished substrate (5 µm x 5 µm area)
Final Epitaxial RMS Roughness	0.18	nm	Thick epitaxial layer (Sample 3)
Substrate Disorientation Angle	3	°	Relative to the (100) plane
Saturated Current Density (J_sat)	200	mA/mm	Highest performance (Sample 3)
On-Resistance (R_on)	95	Ω·mm	Lowest achieved (Sample 3)
J_sat Improvement over Reference	54	%	Comparing Sample 3 (epitaxy) to Sample 1 (polished)
Gate Dielectric Material/Thickness	Al₂O₃ / 50	nm	Deposited by ALD
Ohmic Contact Metal	Au / 50	nm	Deposited by EB evaporation
XRD FWHM (400)	0.015	°	Epitaxial layer (indicates enhanced crystal quality)
Raman FWHM	2.58	cm^-1	Epitaxial layer (indicates reduced stress)

Key Methodologies

The following steps outline the critical MPCVD and processing parameters used to achieve the high-quality epitaxial layer and subsequent MOSFET fabrication:

Substrate Preparation: (100)-oriented CVD diamond substrates (10 mm x 10 mm) with a 3° disorientation angle were cleaned using aqua regia, acetone, alcohol, and deionized water.
Reactor Evacuation: The MPCVD chamber was pumped to a high vacuum of 2 x 10^-5 torr to minimize residual nitrogen gas, crucial for achieving high purity.
Pre-Etching Process: A 30-minute H-plasma pre-etch was performed to remove surface damage and impurities introduced during Chemical Mechanical Polishing (CMP).
- Parameters: 3200 W microwave power, 250 torr pressure.
Epitaxial Growth: High-rate growth (1 hour) was conducted to refill the etch pits created during the pre-etch and achieve an atomically flat surface.
- Parameters: 3600 W microwave power, 300 torr pressure, CH₄/H₂ ratio of 2%.
H-Termination: The diamond surface underwent a fast H-plasma treatment (2600 W, 150 torr) to form the hydrogen-terminated surface necessary for the two-dimensional hole gas (2DHG).
Ohmic Contact Fabrication: 50 nm Au ohmic contacts were deposited via electron beam (EB) evaporation and patterned using photolithography and selective etching (KI solution).
Device Isolation: Electrical isolation was achieved by exposing the unmasked diamond surface to oxygen plasma for 5 minutes.
Gate Stack: A 50 nm Al₂O₃ gate dielectric was deposited using Atomic Layer Deposition (ALD).

6CCVD Solutions & Capabilities

The research successfully demonstrates the necessity of high-quality, low-defect SCD material for advanced diamond electronics. 6CCVD is uniquely positioned to supply the required materials and custom processing services to replicate and scale this research for commercial applications.

Applicable Materials for H-Diamond MOSFETs

To replicate or extend this research, engineers require diamond substrates with exceptional purity, low defect density, and precise orientation control.

6CCVD Material Recommendation	Specification & Relevance to Research
Electronic Grade Single Crystal Diamond (SCD)	Required for high-performance MOSFETs. Our SCD features ultra-low nitrogen content, matching the high purity demonstrated by the absence of N-V centers in the paper’s PL spectra.
Optical Grade Polished SCD Wafers	The paper highlights the critical need for low surface roughness (Ra < 0.18 nm). 6CCVD guarantees Ra < 1 nm standard polishing for SCD, minimizing the initial defects that necessitate complex pre-etching steps.
Custom Off-Angle Substrates	The paper utilized 3° off-angle (100) substrates. 6CCVD provides SCD substrates with precise disorientation angles (e.g., 0.5°, 1.5°, 3°, or custom angles) essential for controlled step-flow growth and pit refilling.

Customization Potential & Processing Services

The complexity of diamond device fabrication requires specialized processing capabilities, all available in-house at 6CCVD.

Custom Dimensions and Thickness:
- The paper used 10 mm x 10 mm samples. 6CCVD can supply SCD wafers up to 125 mm in diameter (PCD) and custom SCD plates, enabling direct scaling for industrial applications.
- We offer precise epitaxial layer thickness control, ranging from 0.1 µm up to 500 µm for SCD, allowing researchers to optimize the 2DHG layer thickness (7 µm used in this study).
Advanced Metalization Services:
- The device utilized Au ohmic contacts and a Ti/Au gate stack (implied by standard H-diamond MOSFET design). 6CCVD offers internal, cleanroom-based metalization capabilities including Au, Pt, Pd, Ti, W, and Cu deposition, tailored to specific device geometries and contact requirements.
Surface Finishing:
- While the paper focused on MPCVD epitaxy to achieve low roughness, 6CCVD offers post-growth polishing services to achieve Ra < 1 nm on SCD and Ra < 5 nm on inch-size PCD, providing alternative routes to atomically flat surfaces.

Engineering Support

The success of this research hinges on optimizing the MPCVD recipe (power, pressure, gas ratio) and the pre-etching process for defect management.

Recipe Optimization: 6CCVD’s in-house PhD material science team specializes in optimizing MPCVD growth recipes for specific applications, including high-rate, low-defect epitaxy required for H-diamond MOSFET projects.
Defect Management Consultation: We provide expert consultation on material selection and processing parameters (e.g., substrate orientation, pre-treatment methods) to minimize defects and maximize carrier mobility and current density in diamond electronic devices.
Global Logistics: 6CCVD ensures reliable, global shipping (DDU default, DDP available) for sensitive diamond materials, supporting international research and development efforts.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

Diamond-based transistors have been considered as one of the best choices due to the numerous advantages of diamond. However, difficulty in the growth and fabrication of diamond needs to be addressed. In this paper, high quality diamond film with an atomically flat surface was grown by microwave plasma chemical vapor deposition. High growth rate, as much as 7 μm/h, has been acquired without nitrogen doping, and the root mean square (RMS) of the surface roughness was reduced from 0.92 nm to 0.18 nm by using a pre-etched process. H-terminated diamond MOSFETs were fabricated on a high-quality epitaxial diamond layer, of which the saturated current density was enhanced. The hysteresis of the transfer curve and the shift of the threshold voltage were significantly reduced as well.

Tech Support

Original Source

DOI: https://doi.org/10.3390/cryst13081221

References

2002 - High Carrier Mobility in Single-Crystal Plasma-Deposited Diamond [Crossref]
2009 - Chemical vapour deposition synthetic diamond: Materials, technology and applications [Crossref]
2020 - 1 W/mm Output Power Density for H-Terminated Diamond MOSFETs With Al2O3/SiO2 Bi-Layer Passivation at 2 GHz [Crossref]
2021 - 1.26 W/mm Output Power Density at 10 GHz for Si3N4 Passivated H-Terminated Diamond MOSFETs [Crossref]
2002 - Some aspects of diamond crystal growth at high temperature and high pressure by TEM and SEM [Crossref]
2002 - Device-grade homoepitaxial diamond film growth [Crossref]
2008 - Bond-Counting Rule for Carbon and its Application to the Roughness of Diamond (001) [Crossref]
2020 - Inversion channel MOSFET on heteroepitaxially grown free-standing diamond [Crossref]
2006 - Diamond FET using high-quality polycrystalline diamond with f/sub T/of 45 GHz and f/sub max/of 120 GHz [Crossref]
2018 - A High Frequency Hydrogen-Terminated Diamond MISFET With fT/fmax of 70/80 GHz [Crossref]