Diamond Metal-Oxide-Semiconductor Field-Effect Transistors on a Large-Area Wafer
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2023-07-21 |
| Authors | Jiangwei Liu, Hirotaka Ohsato, Bo Da, Yasuo Koide |
| Institutions | National Institute for Materials Science |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: Large-Area H-Diamond MOSFETs
Section titled âTechnical Documentation & Analysis: Large-Area H-Diamond MOSFETsâExecutive Summary
Section titled âExecutive SummaryâThis research successfully demonstrates the fabrication and electrical characterization of planar-type and T-type hydrogen-terminated diamond (H-diamond) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) on large-area wafers. This work is critical for pushing diamond electronics toward commercial high-power and high-frequency applications.
- Scalability Validation: MOSFETs were fabricated on large-area 8 x 8 mm2 Ib-type diamond substrates, validating the scalability required for practical electronic devices.
- High-Performance Channel: A 150 nm thick H-diamond homoepitaxial layer was grown via MPCVD, forming the high-mobility p-type channel.
- Structural Optimization: The T-type MOSFET structure proved superior, eliminating interspaces between source/drain and gate electrodes, resulting in significantly improved performance.
- Record Performance Metrics: The T-type device achieved a low on-resistance (RON) of 3.0 x 103 Ω mm and a high maximum drain current (ID,max) of -3.0 mA/mm (at LG = 3.0 ”m).
- Advanced Fabrication: The process utilized complex material stacks, including Pd/Ti/Au Ohmic contacts, a high-k Al2O3/HfSiO2 gate insulator, and Ti/Au gate contacts.
- 6CCVD Relevance: The core materialâhigh-quality, large-area SCD substrates and precise MPCVD epitaxyâis a direct offering from 6CCVD, enabling replication and further scaling of this technology.
Technical Specifications
Section titled âTechnical SpecificationsâThe following table summarizes the key material and performance parameters extracted from the research paper.
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Substrate Material | Ib-type Diamond | (100) | Starting material for epitaxy |
| Wafer Dimension | 8 x 8 x 0.3 | mm3 | Large-area substrate size |
| Epitaxial Layer Thickness | ~150 | nm | H-diamond channel layer |
| MPCVD Deposition Temperature | 900-940 | °C | H-diamond growth recipe |
| MPCVD Chamber Pressure | 80 | Torr | H-diamond growth recipe |
| H2 Flow Rate | 500 | sccm | H-diamond growth recipe |
| CH4 Flow Rate | 0.5 | sccm | H-diamond growth recipe |
| Gate Width (WG) | 100 | ”m | Standard device dimension |
| T-type Max Drain Current (ID,max) | -3.0 | mA/mm | Measured at LG = 3.0 ”m |
| T-type On-Resistance (RON) | 3.0 x 103 | Ω mm | Measured at VGS = -20.0 V |
| Ohmic Contact Stack | 10/20/200 | nm | Pd/Ti/Au metalization |
| Gate Contact Stack | 10/200 | nm | Ti/Au metalization |
Key Methodologies
Section titled âKey MethodologiesâThe fabrication of the H-diamond MOSFETs relied on precise MPCVD growth and advanced semiconductor processing techniques.
- Substrate Cleaning: Ib-type (100) diamond substrate cleaned in H${2}$SO${4}$+HNO$_{3}$ acid solution at 300 °C for 3 hours.
- H-Diamond Homoepitaxy: Growth via Microwave Plasma-Enhanced Chemical Vapor Deposition (MPCVD) using H${2}$ (500 sccm) and CH${4}$ (0.5 sccm) at 900-940 °C and 80 Torr for 1.5 hours, yielding a ~150 nm thick layer.
- Mesa Structure Formation: H-diamond etched in O${2}$ ambient using Capacitively-Coupled Plasma Reactive Ion Etching (RIE) (100 sccm O${2}$, 10 Pa, 50 W source power, 90 s).
- Ohmic Contact Deposition: Source/drain contacts of Pd/Ti/Au (10/20/200 nm) formed using electron-gun evaporation.
- Gate Oxide Deposition: Bilayer insulator deposited: 4.0 nm Al${2}$O${3}$ buffer layer (Atomic Layer Deposition, ALD) followed by HfSiO$_{2}$ high-k layer (Sputtering Deposition, SD).
- Gate Contact Deposition: Ti/Au (10/200 nm) formed via electron-gun evaporation.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & Capabilitiesâ6CCVD is uniquely positioned to supply the high-quality MPCVD diamond materials and custom processing services required to replicate, scale, and advance this high-performance MOSFET research.
| Research Requirement | 6CCVD Solution & Capability | Technical Advantage |
|---|---|---|
| High-Quality (100) Substrates | Electronic Grade SCD Wafers: We provide high-purity Single Crystal Diamond (SCD) substrates optimized for homoepitaxial growth, ensuring minimal defects and high crystalline quality. | Guarantees the low defect density necessary for high carrier mobility and reproducible H-termination results. |
| Large-Area Scalability (8 x 8 mm2) | Custom Dimensions up to 125 mm: While the paper used 8 x 8 mm2, 6CCVD can supply SCD substrates up to 10 mm thick. For future commercial scaling, we offer Polycrystalline Diamond (PCD) plates up to 125 mm diameter. | Enables the transition from laboratory prototypes to commercially viable, large-area power electronics. |
| Precise Epitaxial Layer Control | SCD/PCD Thickness Control: We offer SCD and PCD layers with thicknesses ranging from 0.1 ”m to 500 ”m, grown via highly controlled MPCVD processes. | Ensures precise channel thickness (~150 nm) uniformity, critical for optimizing device characteristics like RON and threshold voltage. |
| Complex Metalization Stacks | In-House Custom Metalization: 6CCVD offers internal deposition capabilities for Au, Pt, Pd, Ti, W, and Cu. We can precisely replicate the required Pd/Ti/Au Ohmic and Ti/Au Gate stacks. | Reduces customer processing complexity and ensures optimal adhesion and contact resistance for Ohmic and Schottky contacts. |
| Surface Finish for H-Termination | Ultra-Smooth Polishing: Our SCD wafers are polished to an industry-leading surface roughness of Ra < 1 nm. | Provides an ideal, damage-free surface necessary for stable H-termination and subsequent high-k dielectric deposition (ALD/SD), minimizing interface scattering. |
6CCVDâs in-house PhD team specializes in material selection and optimization for high-power and high-frequency diamond electronic devices, including H-diamond MOSFETs and Schottky Barrier Diodes (SBDs). We provide expert consultation on doping levels, crystallographic orientation, and surface preparation techniques (e.g., H-termination) to maximize device performance.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
Diamond is promising for high-power, highfrequency, and high-temperature applications.By now, most of diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) are fabricated on small-area diamond wafers (3 Ă 3 mm 2 ).In order to push forward the diamond electronic devices for future practical application, it is necessary to investigate the electrical properties of them on the large-area wafers.In this study, we fabricate planar-type and T-type hydrogen-terminated diamond MOSFETs on a large-area wafer (8 Ă 8 mm 2 ).Electrical properties of them are investigated and discussed.
Tech Support
Section titled âTech SupportâOriginal Source
Section titled âOriginal SourceâReferences
Section titled âReferencesâ- 2008 - Diamond as an electronic material [Crossref]