Bottom-Up Cu Filling of High-Aspect-Ratio through-Diamond vias for 3D Integration in Thermal Management

At a Glance

Metadata	Details
Publication Date	2023-01-22
Journal	Micromachines
Authors	Kechen Zhao, Jiwen Zhao, Xiaoyun Wei, Xiaoyu Guan, Chaojun Deng
Institutions	Harbin Institute of Technology, Huawei Technologies (China)
Citations	9
Analysis	Full AI Review Included

Technical Documentation & Analysis: High-Aspect-Ratio Through-Diamond Vias (TDV) for 3D Thermal Management

This document analyzes the research on bottom-up Cu filling of high-aspect-ratio Through-Diamond Vias (TDV) and outlines how 6CCVD’s advanced MPCVD diamond materials and customization capabilities directly support and enable the replication and scaling of this critical technology for 3D integrated packaging.

Executive Summary

The research successfully demonstrates a robust method for creating highly conductive vertical interconnects in diamond substrates, addressing the critical thermal challenges in high-power 3D integrated circuits (3D-IC).

Material Advantage: Utilizes Polycrystalline Diamond (PCD) with ultra-high thermal conductivity (≥2000 W/mK) as a superior heat spreader layer.
Geometric Achievement: Successfully fabricated and filled high-aspect-ratio (10:1) TDVs with an average longitudinal diameter of 20 µm in 200 µm thick diamond.
Process Innovation: Achieved void-free, bottom-up Cu electroplating through the synergistic use of Ar/O plasma activation and vacuum-assisted prewetting to improve electrolyte wettability.
Electrical Performance: Demonstrated exceptionally low average single-via DC resistance of 47.5 mΩ, confirming suitability for high-speed vertical interconnection.
Thermal Impact: Finite Element Analysis (FEA) simulations show that integrating the TDV layer suppresses hot spot temperatures by approximately 20 °C compared to standard silicon TSV stacks.
Application Focus: Provides a promising pathway for developing advanced diamond substrates for thermal management in high-power semiconductor devices and 3D integrated packaging.

Technical Specifications

The following hard data points were extracted from the research paper detailing the material properties and performance metrics of the Cu-filled TDVs.

Parameter	Value	Unit	Context
Diamond Thermal Conductivity	≥2000	W/mK	Bulk material property
Diamond Substrate Thickness	200 ± 20	µm	Material used for TDV fabrication
TDV Aspect Ratio	10:1	Ratio	Achieved via geometry (Depth:Diameter)
TDV Average Longitudinal Diameter	~20	µm	Measured via geometry
Single-Via DC Resistance (Average)	47.5	mΩ	Low interconnection resistance achieved
Optimal Electroplating Current Density	0.3	ASD	Used for void-free bottom-up filling
Laser Wavelength (Drilling)	355	nm	UV nanosecond laser system
Plasma Treatment Power	300	W	Ar/O hybrid plasma activation
Contact Angle (TDV Surface, Treated)	~47	°	Improved wettability for electroplating
Simulated Hot Spot Suppression	~20	°C	Comparing TDV integration vs. Si TSV stack

Key Methodologies

The fabrication of the high-aspect-ratio Cu-filled TDVs involved precise material preparation, laser processing, surface modification, and optimized electroplating.

Substrate Preparation: Polycrystalline diamond chips (10 x 10 mm²) with a thickness of 200 ± 20 µm were polished to an ultra-smooth surface.
Via Fabrication: Through-vias were drilled using a UV nanosecond laser processing system (355 nm wavelength, 15 W power, 40 kHz repetition rate, 12 ns pulse width).
Conductive Layer Deposition: A Cr/Au layer was double-sided deposited via Physical Vapor Deposition (PVD) to serve as the seed layer for electroplating and the bonding layer.
Temporary Bonding: The diamond was temporarily bonded to Au-deposited quartz flakes via hot pressing (5 MPa, 200 °C, 10 min).
Surface Pretreatment: Synergistic Ar/O hybrid plasma treatment (300 W for 2 min) was applied to the TDV surface to improve electrolyte wettability, followed by vacuum-assisted prewetting.
Bottom-Up Cu Electroplating: A Direct Current (DC) source was used in a standard copper sulfate electrolyte bath containing proprietary additives (accelerator, inhibitor, leveler). Optimal filling was achieved at a current density of 0.3 ASD.
Characterization: TDV morphology, filling quality, and stress were analyzed using SEM, EDS, 2D/3D CT scans, and Raman spectroscopy. Electrical performance was measured using the Kelvin Four-Point Probe (4PP) method.

6CCVD Solutions & Capabilities

6CCVD is uniquely positioned to supply the high-quality MPCVD diamond materials and custom engineering services required to replicate, scale, and advance this research into commercial applications for high-power thermal management.

Applicable Materials

The paper utilized Polycrystalline Diamond (PCD) for its high thermal conductivity. 6CCVD offers both PCD and Single Crystal Diamond (SCD) options, allowing researchers to optimize performance based on cost and thermal requirements.

Thermal Grade Polycrystalline Diamond (PCD):
- Recommendation: Ideal for replicating the reported study and scaling to larger formats (up to 125mm wafers).
- Benefit: Provides thermal conductivity exceeding 1800 W/mK, matching the performance required for high-power heat spreading.
Electronic Grade Single Crystal Diamond (SCD):
- Recommendation: For next-generation devices requiring maximum thermal performance and ultra-low defect density.
- Benefit: Offers superior thermal properties (often >2200 W/mK) and higher purity, crucial for minimizing stress and maximizing reliability in complex 3D stacks.
Thickness Range: 6CCVD can supply substrates matching the paper’s requirement (200 µm) and extend up to 500 µm (PCD/SCD) or up to 10mm (Substrates) for robust packaging solutions.

Customization Potential

The success of the TDV process relies heavily on precise substrate dimensions, surface quality, and conductive layer integrity—all core competencies of 6CCVD.

Research Requirement	6CCVD Capability	Value Proposition
Substrate Size (10 x 10 mm²)	Custom dimensions up to 125mm (PCD)	Enables scaling from R&D prototypes to production-ready wafer sizes.
Thickness Control (200 ± 20 µm)	SCD/PCD thickness control from 0.1 µm to 500 µm	Guaranteed tight tolerance control for precise 3D stacking and bonding processes.
Surface Quality (Ultra-smooth)	Polishing to Ra < 5nm (PCD) or Ra < 1nm (SCD)	Provides the necessary ultra-smooth surface required for subsequent lithography, PVD, and low-resistance bonding interfaces (TIR).
Metalization (Cr/Au seed layer)	In-house PVD capability (Au, Pt, Pd, Ti, W, Cu)	We offer custom metal stacks (e.g., Ti/Pt/Au or Cr/Au) optimized for adhesion, barrier function, and compatibility with specific electroplating chemistries.
Post-Processing (Via Definition)	Laser cutting and dicing services	Provides custom shaping and precise singulation of diamond chips after TDV fabrication.

Engineering Support

6CCVD’s in-house team of PhD material scientists specializes in optimizing diamond properties for demanding electronic and thermal applications. We provide comprehensive support for projects involving:

High-Power Thermal Management: Assisting in material selection (SCD vs. PCD) and thickness optimization to achieve target thermal resistance (TIR) reduction.
3D Integration and Interconnects: Consulting on surface preparation and metalization schemes to ensure optimal adhesion and electrical performance for subsequent processes like electroplating and hybrid bonding.
Stress Mitigation: Providing expertise on how diamond grain size and orientation affect internal stress distribution (as highlighted by the Raman analysis in the paper) when integrating materials with disparate Coefficients of Thermal Expansion (CTE), such as Cu.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

Three-dimensional integrated packaging with through-silicon vias (TSV) can meet the requirements of high-speed computation, high-density storage, low power consumption, and compactness. However, higher power density increases heat dissipation problems, such as severe internal heat storage and prominent local hot spots. Among bulk materials, diamond has the highest thermal conductivity (≥2000 W/mK), thereby prompting its application in high-power semiconductor devices for heat dissipation. In this paper, we report an innovative bottom-up Cu electroplating technique with a high-aspect-ratio (10:1) through-diamond vias (TDV). The TDV structure was fabricated by laser processing. The electrolyte wettability of the diamond and metallization surface was improved by Ar/O plasma treatment. Finally, a Cu-filled high-aspect-ratio TDV was realized based on the bottom-up Cu electroplating process at a current density of 0.3 ASD. The average single-via resistance was ≤50 mΩ, which demonstrates the promising application of the fabricated TDV in the thermal management of advanced packaging systems.

Tech Support

Original Source

DOI: https://doi.org/10.3390/mi14020290

References

2010 - Wafer-Level bonding/stacking technology for 3D integration [Crossref]
2019 - Highly Efficient GaN-Based High-Power Flip- Chip Light-Emitting Diodes [Crossref]
2015 - 21-layer 3D chip stacking based on Cu-Sn bump bonding [Crossref]
2022 - MOSFETs on (110) C-H Diamond: ALD Al2O3/Diamond Interface Analysis and High Performance Normally-OFF Operation Realization [Crossref]
2019 - Microsystems Using Three-Dimensional Integration and TSV Technologies: Fundamentals and Applications [Crossref]
2021 - Ultra-high-performance heat spreader based on a graphite architecture with three-dimensional thermal routing [Crossref]
2014 - Review and projections of integrated cooling systems for three-dimensional integrated circuits [Crossref]