Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2022-09-17 |
| Journal | Journal of Integrated Circuits and Systems |
| Authors | Gabriel Augusto DaSilva, Salvador Pinillos Gimenez |
| Institutions | Centro UniversitĂĄrio FEI |
| Citations | 4 |
| Analysis | Full AI Review Included |
Technical Analysis and Documentation: Innovative MOSFET Layouts for Analog CMOS
Section titled âTechnical Analysis and Documentation: Innovative MOSFET Layouts for Analog CMOSâExecutive Summary
Section titled âExecutive SummaryâThis document analyzes the experimental validation of the Half-Diamond (HDM) MOSFET layout style, an element of the second generation of innovative geometries designed to boost analog and RF circuit performance. 6CCVD leverages its expertise in high-purity MPCVD diamond to offer materials that maximize the benefits of these advanced layouts, particularly in high-power and radiation-hardened applications.
- Core Achievement: Introduction and experimental validation of the Half-Diamond (HDM) layout, demonstrating superior electrical performance compared to conventional (CM) and first-generation Diamond (DM) layouts.
- Performance Gains: HDM achieved a 17% higher normalized saturation drain current ($I_{DSsat}$) and a 3.5% higher low-frequency open-loop voltage gain ($A_{v0}$) compared to CM counterparts.
- Key Figures of Merit: Significant improvements were observed in dynamic parameters, including maximum transconductance ($g_{mmax}$) and unit voltage gain frequency ($f_T$), both exceeding 22% higher than CM1.
- Physical Mechanisms: Enhanced performance is attributed to the Longitudinal Corner Effect (LCE) and the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), which effectively reduce the channel length ($L_{eff}$).
- Application Focus: The HDM layout is proposed as a simple, low-cost alternative to further improve the electrical performance of analog MOSFETs and CMOS ICs, especially where high-frequency operation and ionizing radiation tolerance are critical.
- Technology Context: Results were validated using the 180 nm Bulk CMOS ICs technology node.
Technical Specifications
Section titled âTechnical SpecificationsâThe following table summarizes the key experimental data and performance metrics extracted from the comparative study of the Half-Diamond MOSFET (HDM) against its counterparts (DM, CM1, CM2).
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Technology Node | 180 | nm | Bulk CMOS ICs (TSMC/IMEC) |
| Matched Gate Area ($A_G$) | 0.46 | ”m2 | HDM, DM, and CM1 |
| Effective Channel Length ($L_{eff}$) (HDM) | 0.37 | ”m | Reduced by PAMDLE effect |
| $I_{DSsat}/(W/L_{geo})$ (HDM) | 10.7 | ”A | Normalized saturation drain current @ $V_{GT}=100$ mV |
| $I_{DSsat}/(W/L_{geo})$ Gain (HDM vs. CM1) | 17.2 | % | Improvement in saturation current |
| $I_{DS}/(W/L_{geo})$ (HDM, Triode) | 30.3 | ”A | @ $V_{DS}=100$ mV, $V_{GT}=0.8$ V |
| $g_{mmax}/(W/L_{geo})$ Gain (HDM vs. CM1) | 22.2 | % | Improvement in maximum transconductance |
| $f_T/(W/L_{geo})$ Gain (HDM vs. CM1) | 22.2 | % | Improvement in unit voltage gain frequency |
| Low-Frequency Voltage Gain ($\Delta A_{v0}$) (HDM vs. CM1) | 3.5 | % | Improvement in $A_{v0}$ (dB) |
| On-State Resistance $R_{ON} \cdot (L_{geo}/W)$ Reduction (HDM vs. CM1) | 32.4 | % | Reduction in normalized on-state resistance |
| Threshold Voltage ($V_{TH}$) (HDM) | 0.460 | V | Consistent across all devices (± 0.002 V) |
Key Methodologies
Section titled âKey MethodologiesâThe experimental study relied on precise fabrication and comparative measurement techniques to validate the performance benefits of the Half-Diamond layout style.
- Device Fabrication: MOSFETs (HDM, DM, CM1, CM2) were manufactured using the 180 nm Bulk CMOS ICs technology node via the Taiwan Semiconductor Manufacturing Company (TSMC) and Interuniversity Microelectronics Centre (IMEC).
- Layout Design: The HDM layout features a hybrid gate geometry composed of a triangular part (Diamond) in the drain region and a rectangular part (Conventional) in the source region, designed to minimize the B dimension and reduce die area.
- Comparative Study: Devices were designed to present the same gate area ($A_G = 0.46$ ”m2) and were tested under identical bias conditions to ensure a fair comparison of layout effects.
- Parameter Normalization: Electrical parameters and figures of merit were normalized by the geometric aspect ratio ($W/L_{geo}$) to properly account for the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE).
- Performance Metrics: Key measurements included the transfer characteristics ($I_{DS}$ vs. $V_{GT}$) and output characteristics ($I_{DS}$ vs. $V_{DS}$), focusing on saturation current ($I_{DSsat}$), transconductance ($g_{mmax}$), and frequency response ($f_T$).
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThe research demonstrates that advanced layout engineering significantly boosts the performance of analog MOSFETs, particularly in high-frequency and radiation-hardened applications. While this study used silicon CMOS, the ultimate performance ceiling for such devices is achieved using diamondâthe material of choice for extreme environments and high-power RF electronics.
6CCVD provides the foundational MPCVD diamond materials and precision engineering services necessary to replicate, extend, and maximize the benefits of innovative layout styles like Half-Diamond in next-generation devices.
Applicable Materials
Section titled âApplicable MaterialsâTo extend this research into high-power, high-frequency, or extreme environment applications, 6CCVD recommends the following materials:
- Electronic Grade Single Crystal Diamond (SCD): Ideal for high-mobility, high-frequency RF MOSFETs. SCD offers the highest thermal conductivity (>2000 W/mK), ensuring superior heat dissipation, which is critical for maximizing the current density gains achieved by the HDM layout.
- Recommendation: SCD plates up to 500 ”m thick, polished to Ra < 1 nm for optimal interface quality.
- Polycrystalline Diamond (PCD) Substrates: Suitable for large-area, high-power analog integrated circuits where the innovative layout must be scaled. PCD offers excellent thermal management at a lower cost than SCD.
- Recommendation: PCD wafers available in custom dimensions up to 125 mm in diameter.
- Boron-Doped Diamond (BDD): Essential for creating highly conductive, radiation-hard electrodes or active device layers, leveraging diamondâs inherent resistance to Total Ionizing Dose (TID) effects (DEPAMBBRE).
Customization Potential
Section titled âCustomization PotentialâThe Half-Diamond and other innovative layouts (Diamond, Octo, Ellipsoidal) require precise, non-conventional geometries that standard silicon foundries struggle to deliver in exotic materials. 6CCVD specializes in the precision engineering required for these advanced designs.
| Custom Requirement (Based on Paper) | 6CCVD Capability | Benefit to Research |
|---|---|---|
| Complex Gate Shapes | Precision Laser Cutting & Etching | Realization of sub-micron, non-rectangular geometries (Half-Diamond, Octagonal) on SCD and PCD wafers. |
| Specific Channel Dimensions | Custom Dimensions & Thickness Control | SCD and PCD materials available in thicknesses from 0.1 ”m to 500 ”m, and substrates up to 10 mm, allowing precise control over device scaling and $L_{eff}$. |
| Ohmic/Schottky Contacts | In-House Metalization Services | Deposition of custom metal stacks (Au, Pt, Pd, Ti, W, Cu) required for high-performance analog contacts and interconnects, ensuring low contact resistance ($R_{ON}$). |
| Surface Quality | Advanced Polishing Services | Guaranteed surface roughness of Ra < 1 nm (SCD) and Ra < 5 nm (PCD) to minimize scattering and maximize carrier mobility at the gate interface. |
Engineering Support
Section titled âEngineering SupportâThe successful implementation of innovative layout strategies, such as HDM, in diamond-based devices requires deep material and device physics knowledge. 6CCVDâs in-house PhD engineering team offers comprehensive support:
- Material Selection: Assistance in selecting the optimal SCD or PCD grade to maximize the LCE and PAMDLE effects for specific high-frequency or high-power analog MOSFET projects.
- Process Integration: Consultation on metalization schemes and surface preparation techniques necessary for integrating complex gate structures onto diamond substrates.
- Application Extension: Support for projects targeting extreme environments, leveraging diamondâs radiation hardness to enhance the Deactivation of Parasitic MOSFETs in Birdâs Beaks Regions (DEPAMBBRE) effect observed in this research.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Birdâs Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.