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6CCVD Research

SiGeSn Quantum Dots in HfO2 for Floating Gate Memory Capacitors

At a Glance

Section titled “At a Glance”
MetadataDetails
Publication Date2022-03-07
JournalCoatings
AuthorsCătălin Palade, A. Slav, Ovidiu Cojocaru, V. S. Teodorescu, T. Stoïca
InstitutionsAcademy of Romanian Scientists, University of Bucharest
Citations12
AnalysisFull AI Review Included

Technical Documentation & Analysis: SiGeSn Quantum Dots for Floating Gate Memory Capacitors

Section titled “Technical Documentation & Analysis: SiGeSn Quantum Dots for Floating Gate Memory Capacitors”

Executive Summary

Section titled “Executive Summary”

This document analyzes the fabrication and performance of Non-Volatile Memory (NVM) capacitors utilizing SiGeSn Quantum Dots (QDs) embedded in HfO2, a highly CMOS-compatible high-k dielectric system.

  • Core Achievement: Successful demonstration of high-density floating gate memory capacitors based on a Gate HfO2/SiGeSn-HfO2/Tunnel HfO2/p-Si trilayer stack fabricated via magnetron sputtering and Rapid Thermal Annealing (RTA).
  • Optimal Performance: Maximum memory windows of 3-4 V and stored electron densities reaching 1-2 × 1013 electrons/cm2 were achieved at optimal RTA temperatures (520-530 °C).
  • Material Advantage: The inclusion of Sn lowers the crystallization temperature of SiGeSn QDs (to 520-530 °C RTA), enabling a low thermal budget process highly suitable for CMOS integration.
  • Dual QD Formation: Optimal annealing results in two distinct crystalline QD types: low Sn content (2 at.%) QDs within the floating gate, and high Sn content (up to 12.5 at.%) QDs concentrated at the HfO2 interfaces.
  • 6CCVD Value Proposition: While this research uses Si substrates, 6CCVD provides the ideal platform—Single Crystal Diamond (SCD) and Polycrystalline Diamond (PCD)—to integrate these high-performance memory structures onto wide-bandgap (WBG) substrates, enabling operation in extreme environments (high temperature, radiation) and leveraging diamond’s superior thermal management for high-density NVM arrays.

Technical Specifications

Section titled “Technical Specifications”
ParameterValueUnitContext
Optimal RTA Temperature520 - 530°CTemperature range yielding highest memory window.
Optimal RTA Duration5minDuration yielding highest stored electron density.
Maximum Memory Window ($\Delta V_{FB}$)4.0VAchieved on M1 structure (530 °C, 5 min RTA).
Maximum Stored Electron Density ($n$)2.0 × 1013electrons/cm2Achieved on M1 structure (530 °C, 5 min RTA).
High Sn QD ContentUp to 12.5at.%Located at the floating gate/HfO2 interfaces.
Low Sn QD Content~2at.%Located inside the floating gate layer.
QD Diameter (Estimated)~5nmDiameter of Ge-rich SiGeSn QDs.
Gate Oxide Thickness (Designed M1)16 - 17nmHfO2 layer thickness.
Floating Gate Thickness (Designed M1)9 - 10nmSiGeSn-HfO2 intermediate layer thickness.
Tunnel Oxide Thickness (Designed M1)7 - 8nmHfO2 layer thickness on p-Si.
Electrode Area1 × 1mm2Area of top Al contacts.

Key Methodologies

Section titled “Key Methodologies”

The fabrication process relies on precise thin-film deposition and controlled thermal processing to achieve nanocrystallization and QD formation.

  1. Substrate Preparation: (100) p-Si substrates (7-14 Ωcm resistivity) were chemically cleaned using standard procedures.
  2. Tunnel Oxide Deposition: Thin HfO2 (4-8 nm) was deposited via magnetron sputtering (45-55 W RF power).
  3. Floating Gate Deposition (Intermediate Layer): Co-deposition via magnetron sputtering of SiGe (25-35 W DC), Sn (3.5-10 W DC), and HfO2.
    • Designed Composition: 10% Sn: 90% SiGe (vol.) and 80% SiGeSn: 20% HfO2 (vol.).
    • SiGe Target Composition: 5% Si: 95% Ge (at.).
  4. Gate Oxide Deposition: Thick HfO2 (16-21 nm) was deposited via magnetron sputtering.
  5. Nanostructuring: Rapid Thermal Annealing (RTA) in N2 (6N purity) atmosphere.
    • Temperature Range: 325-600 °C.
    • Duration Range: 2-15 min.
  6. Electrode Deposition: Top and bottom Al electrodes were deposited using thermal evaporation through shadow masks (1 mm × 1 mm area).
  7. Characterization: Crystalline structure, morphology, and composition were analyzed using HRTEM, XRD, Raman spectroscopy, and C-V hysteresis measurements.

6CCVD Solutions & Capabilities

Section titled “6CCVD Solutions & Capabilities”

This research demonstrates a high-performance memory architecture suitable for CMOS integration and future photonic flash memories (due to SiGeSn’s SWIR sensitivity). 6CCVD specializes in providing the foundational diamond materials and advanced processing required to transition such high-performance devices to next-generation, extreme-environment platforms.

Applicable Materials

Section titled “Applicable Materials”

To replicate or extend this research onto a wide-bandgap platform, 6CCVD recommends the following materials, leveraging diamond’s superior thermal, electrical, and radiation hardness properties:

6CCVD MaterialRecommended SpecificationApplication in NVM Research
Optical Grade SCDSCD, Ra < 1 nm, 100 μm - 500 μm thicknessIdeal substrate for high-quality epitaxial growth of HfO2/SiGeSn stacks, maximizing interface quality and thermal dissipation.
Electronic Grade PCDPCD, up to 125 mm diameter, Ra < 5 nmCost-effective, large-area platform for high-density NVM array integration where single-crystal perfection is not strictly required.
Heavy Boron Doped Diamond (BDD)SCD or PCD, highly conductive (p-type)Replacement for the p-Si substrate or as a highly stable, conductive bottom electrode, enabling high-temperature operation and enhanced charge injection stability.

Customization Potential

Section titled “Customization Potential”

The success of the SiGeSn QD memory relies heavily on precise layer thickness control and electrode quality. 6CCVD offers specialized services critical for optimizing these structures on diamond platforms:

  • Custom Dimensions: 6CCVD provides custom plates and wafers up to 125 mm (PCD) and custom thicknesses for SCD (0.1 μm - 500 μm) and substrates (up to 10 mm), allowing researchers to scale device geometry beyond the 1 mm × 1 mm contacts used in the paper.
  • Advanced Polishing: Achieving the ultra-smooth surfaces required for uniform thin-film deposition (like HfO2 and SiGeSn) is paramount. 6CCVD guarantees surface roughness of Ra < 1 nm for SCD and Ra < 5 nm for inch-size PCD.
  • Custom Metalization: While the paper used Al electrodes, 6CCVD offers in-house metalization services including Ti, Pt, Au, Pd, W, and Cu. Utilizing stable, high-work-function metals (e.g., Ti/Pt/Au stacks) is essential for optimizing contact resistance and stability in high-k dielectric MOS structures, especially when integrating onto BDD.
  • Laser Cutting & Shaping: Precision laser cutting services ensure custom shapes and geometries for complex device integration.

Engineering Support

Section titled “Engineering Support”

The transition of SiGeSn QD memory technology from Si to a diamond platform requires specialized material science expertise. 6CCVD’s in-house PhD team can assist with material selection, interface engineering, and process optimization for similar Floating Gate Memory or SWIR Photonic Flash Memory projects. We provide consultation on:

  • Optimizing BDD conductivity for use as a stable charge injection layer.
  • Selecting appropriate metalization schemes to minimize diffusion and maximize adhesion to both diamond and HfO2 layers.
  • Determining optimal diamond substrate orientation and surface termination for subsequent high-k dielectric deposition.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

Group IV quantum dots (QDs) in HfO2 are attractive for non-volatile memories (NVMs) due to complementary metal-oxide semiconductor (CMOS) compatibility. Besides the role of charge storage centers, SiGeSn QDs have the advantage of a low thermal budget for formation, because Sn presence decreases crystallization temperature, while Si ensures higher thermal stability. In this paper, we prepare MOS capacitors based on 3-layer stacks of gate HfO2/floating gate of SiGeSn QDs in HfO2/tunnel HfO2/p-Si obtained by magnetron sputtering deposition followed by rapid thermal annealing (RTA) for nanocrystallization. Crystalline structure, morphology, and composition studies by cross-section transmission electron microscopy and X-ray diffraction correlated with Raman spectroscopy and C-V measurements are carried out for understanding RTA temperature effects on charge storage behavior. 3-layer morphology and Sn content trends with RTA temperature are explained by the strongly temperature-dependent Sn segregation and diffusion processes. We show that the memory properties measured on Al/3-layer stack/p-Si/Al capacitors are controlled by SiGeSn-related trapping states (deep electronic levels) and low-ordering clusters for RTA at 325-450 °C, and by crystalline SiGeSn QDs for 520 and 530 °C RTA. Specific to the structures annealed at 520 and 530 °C is the formation of two kinds of crystalline SiGeSn QDs, i.e., QDs with low Sn content (2 at.%) that are positioned inside the floating gate, and QDs with high Sn content (up to 12.5 at.%) located at the interface of floating gate with adjacent HfO2 layers. The presence of Sn in the SiGe intermediate layer decreases the SiGe crystallization temperature and induces the easier crystallization of the diamond structure in comparison with 3-layer stacks with Ge-HfO2 intermediate layer. High frequency-independent memory windows of 3-4 V and stored electron densities of 1-2 × 1013 electrons/cm2 are achieved.

Tech Support

Section titled “Tech Support”

Original Source

Section titled “Original Source”

References

Section titled “References”
  1. 2020 - Semiconductor quantum dots for memories and neuromorphic computing systems [Crossref]
  2. 2018 - A review on Ge nanocrystals embedded in SiO2 and high-k dielectrics [Crossref]
  3. 2016 - Effect of hydrogen ion beam treatment on Si nanocrystal/SiO2 superlattice-based memory devices [Crossref]
  4. 2016 - Germanium nanoparticles grown at different deposition times for memory device applications [Crossref]
  5. 2012 - Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing [Crossref]
  6. 2011 - Carbon nanotube memory by the self-assembly of silicon nanocrystals as charge storage nodes [Crossref]
  7. 2019 - Self-assembled Sn nanocrystals as the floating gate of nonvolatile flash memory [Crossref]
  8. 2016 - Non-volatile memory devices based on Ge nanocrystals [Crossref]
  9. 2016 - Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals [Crossref]
  10. 2015 - Multilayer Ge nanocrystals embedded within Al2O3 matrix for high performance floating gate memory devices [Crossref]

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