Electrical Characteristics of Diamond MOSFET with 2DHG on a Heteroepitaxial Diamond Substrate

At a Glance

Metadata	Details
Publication Date	2022-03-31
Journal	Materials
Authors	Genqiang Chen, Wei Wang, Fang Lin, Minghui Zhang, Qiang Wei
Institutions	Hebei Semiconductor Research Institute, Xi’an Jiaotong University
Citations	5
Analysis	Full AI Review Included

Technical Analysis and Documentation: Diamond MOSFETs on Heteroepitaxial Substrates

Executive Summary

This document analyzes the fabrication and characterization of a high-performance hydrogen-terminated diamond (H-diamond) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) built on a heteroepitaxial single crystal diamond (HSCD) substrate. The results validate the potential for scaling diamond electronics using large-area heteroepitaxy, a key focus area for 6CCVD.

Core Achievement: Successful demonstration of a high-performance H-diamond MOSFET on a free-standing HSCD substrate (26 × 26 × 1 mm³), promoting cost reduction and mass production capability.
Performance Metrics: Achieved a maximum output current density (I_DS) of 172 mA/mm and a peak transconductance (g_m(max)) of 10.4 mS/mm.
Material Quality: The HSCD substrate exhibited a (004) X-ray rocking curve FWHM of 209.52 arcsec, demonstrating high crystalline quality for heteroepitaxial growth.
Mobility Enhancement: A low-temperature annealing process (423 K, N₂ atmosphere) increased the hole field effective mobility (µ_eff) by 27%, reaching 46.5 cm²/Vs, attributed to the reduction of interface state density (D_it).
Device Structure: The device utilized a robust ALD-Al₂O₃ dielectric layer (30 nm total thickness) and a Ti/Au gate electrode, confirming compatibility with standard semiconductor processing techniques.
6CCVD Value Proposition: 6CCVD specializes in providing high-quality, large-area SCD and PCD substrates, often exceeding the crystalline quality of the heteroepitaxial material used in this study, enabling superior device performance and scalability.

Technical Specifications

The following table summarizes the critical material and electrical performance parameters extracted from the research.

Parameter	Value	Unit	Context
Substrate Type	Heteroepitaxial SCD (HSCD)	N/A	Grown on Ir/a-plane sapphire
Substrate Dimension	26 × 26 × 1	mm³	Free-standing
X-ray Rocking Curve FWHM (004)	209.52	arcsec	Material quality metric
Max Output Current Density (I_DS)	172	mA/mm	At V_GS = -8 V; V_DS = -30 V
Max Transconductance (g_m(max))	10.4	mS/mm	Peak device performance
On-Resistance (R_ON)	130.5	Ω·mm	Device efficiency
Carrier Density (p)	3.3 × 10¹³	/cm²	At V_GS = -8 V
Effective Mobility (µ_eff) (RT)	36.5	cm²/Vs	Measured at room temperature
Effective Mobility (µ_eff) (Annealed)	46.5	cm²/Vs	After 423 K annealing (27% increase)
Interface State Density (D_it) (RT)	1.07 × 10¹³	eV⁻¹/cm²	Calculated from subthreshold swing
Gate Dielectric Thickness	30	nm	ALD-Al₂O₃ (5 nm + 25 nm layers)
Subthreshold Slope (SS)	400	mV/dec	Device switching speed
On/Off Ratio	>10⁵	N/A	Device isolation performance

Key Methodologies

The device fabrication relied heavily on MPCVD for diamond growth and Atomic Layer Deposition (ALD) for the high-quality gate dielectric.

Substrate Preparation:
- a-plane (11-20) sapphire (26 × 26 × 1 mm³) was used as the initial template.
- 150 nm Ir buffer layer deposited at 900 °C via magnetron sputtering.
- Bias Enhanced Nucleation (BEN) conducted in DC CVD.
Heteroepitaxial Growth:
- Horizontal type MPCVD used for 100 h, achieving a growth rate of 10 µm/h.
Homoepitaxial Layer Growth:
- 100 nm homoepitaxial layer grown on the HSCD using MPCVD.
- Growth Parameters: Temperature: 930~970 °C; Pressure: 30 Torr; Time: 60 min.
- Gas Flow: H₂: 300 sccm; CH₄: 0.6 sccm.
H-Termination and Metalization (S/D):
- Hydrogen plasma maintained for 20 min to form the H-diamond surface.
- 200 nm Au deposited via electron beam evaporation for Source and Drain electrodes.
Passivation and Dielectric Deposition:
- UV/O₃ treatment used to convert H-termination to Oxygen-termination (OT) outside the channel region.
- Al₂O₃ dielectric deposited via ALD (Trimethylaluminum (TMA) and H₂O sources) in two steps:
  - 5 nm Al₂O₃ layer deposited at 90 °C (C-H protection).
  - 25 nm Al₂O₃ layer deposited at 250 °C.
Gate Electrode Deposition:
- 30/150 nm Ti/Au stack deposited on the Al₂O₃ layer.
Post-Fabrication Annealing:
- Low-temperature annealing performed in N₂ atmosphere at 423 K (150 °C) and 473 K (200 °C) for 3 min to optimize interface quality.

6CCVD Solutions & Capabilities

The successful fabrication of high-performance diamond MOSFETs relies on ultra-high quality diamond substrates and precise material engineering. 6CCVD is uniquely positioned to supply and enhance the materials required for replicating and advancing this research.

Applicable Materials

To achieve or surpass the performance reported in this study, researchers require high-quality, low-dislocation SCD substrates.

6CCVD Material Solution	Specification & Advantage	Application Relevance
Electronic Grade SCD	High purity, low nitrogen content, FWHM typically < 50 arcsec (significantly lower than the 209.52 arcsec reported for HSCD).	Essential for minimizing scattering and maximizing hole mobility (µ_eff) in the 2DHG channel.
Optical Grade SCD	Available in thicknesses from 0.1 µm up to 500 µm, suitable for thin-film device layers.	Ideal for the 100 nm homoepitaxial layer required for the H-diamond surface conductivity.
Large-Area PCD	Available up to 125 mm diameter. While the paper focused on HSCD scaling, PCD offers the ultimate path to wafer-scale, low-cost manufacturing for non-SCD-critical applications.	Enables future large-scale commercialization of diamond power electronics and sensors.

Customization Potential

6CCVD’s in-house engineering capabilities directly address the specific material processing steps detailed in the paper, offering turnkey solutions for device fabrication.

Custom Dimensions: The paper used 26 × 26 mm³ substrates. 6CCVD provides custom-cut plates and wafers, ensuring precise dimensions for specific lithography and processing tools. We offer substrates up to 10 mm thick.
Advanced Metalization: The device utilized Ti/Au electrodes. 6CCVD offers internal metalization services, including:
- Gate/Ohmic Contacts: Custom deposition of Ti/Au (as used here), Pt, Pd, or W stacks, tailored for optimal ohmic contact and thermal stability.
- Dielectric Compatibility: Metalization can be performed post-ALD simulation to ensure compatibility with the Al₂O₃ dielectric layer.
Surface Engineering: The quality of the H-diamond/Al₂O₃ interface is critical (as shown by the D_it dependence on annealing).
- Polishing: 6CCVD guarantees ultra-smooth SCD surfaces (Ra < 1 nm) and inch-size PCD surfaces (Ra < 5 nm), which are crucial for minimizing interface traps and maximizing the effectiveness of ALD dielectrics.
- Termination Control: We provide substrates with controlled surface terminations (H-terminated or O-terminated) ready for immediate device processing.

Engineering Support

6CCVD’s in-house PhD team possesses deep expertise in MPCVD growth parameters, surface physics, and electronic device integration. We offer consultation services to optimize material selection for high-frequency, high-power applications like the H-diamond MOSFET described. We can assist researchers in determining the optimal thickness, crystalline orientation, and surface preparation necessary to achieve target mobility and breakdown voltage metrics for similar 2DHG Diamond MOSFET projects.

Call to Action: For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

In this work, hydrogen-terminated diamond (H-diamond) metal-oxide-semiconductor field-effect-transistors (MOSFETs) on a heteroepitaxial diamond substrate with an Al2O3 dielectric and a passivation layer were characterized. The full-width at half maximum value of the diamond (004) X-ray rocking curve was 205.9 arcsec. The maximum output current density and transconductance of the MOSFET were 172 mA/mm and 10.4 mS/mm, respectively. The effect of a low-temperature annealing process on electrical properties was also investigated. After the annealing process in N2 atmosphere, the threshold voltage (Vth) and flat-band voltage (VFB) shifts to negative direction due to loss of negative charges. After annealing at 423 K for 3 min, the maximum value of hole field effective mobility (μeff) increases by 27% at Vth − VGS = 2 V. The results, which are not inferior to those based on homoepitaxial diamond, promote the application of heteroepitaxial diamond in the field of electronic devices.

Tech Support

Original Source

DOI: https://doi.org/10.3390/ma15072557

References

1992 - Some aspects of the thermal conductivity of isotopically enriched diamond single crystals [Crossref]
2002 - High Carrier Mobility in Single-Crystal Plasma-Deposited Diamond [Crossref]
1981 - Hole-drift velocity in natural diamond [Crossref]
2000 - Origin of surface conductivity in diamond [Crossref]
1996 - Hydrogen-terminated diamond surfaces and interfaces [Crossref]
1996 - Electrically Isolated Metal-Semiconductor Field Effect Transistors and Logic Circuits on Homoepitaxial Diamonds [Crossref]
2012 - Diamond Field-Effect Transistors with 1.3 A/mm Drain Current Density by Al2O3 Passivation Layer [Crossref]
2006 - Diamond FET Using High-Quality Polycrystalline [Crossref]
2019 - 3.8 W/mm RF Power Density for ALD Al2O3-Based Two-Dimensional Hole Gas Diamond MOSFET Operating at Saturation Velocity [Crossref]
2017 - Ion bombardment induced buried lateral growth: The key mechanism for the synthesis of single crystal diamond wafers [Crossref]