Characteristics of hydrogen terminated single crystalline diamond logic inverter

At a Glance

Metadata	Details
Publication Date	2022-01-01
Journal	Acta Physica Sinica
Authors	Yufei Xing, Zeyang Ren, Jinfeng Zhang, Kai Su, Senchuan Ding
Institutions	Xidian University, Wuhu Institute of Technology
Citations	6
Analysis	Full AI Review Included

6CCVD Technical Analysis: Hydrogen-Terminated Single Crystal Diamond Logic Inverter

This document analyzes the research detailing the fabrication and characterization of a high-performance hydrogen-terminated Single Crystal Diamond (SCD) MOSFET logic inverter, establishing the commercial potential for 6CCVD’s advanced MPCVD diamond materials in digital electronics.

Executive Summary

This research successfully demonstrates a functional depletion-mode logic inverter based on a hydrogen-terminated Single Crystal Diamond (H-Diamond) MOSFET and integrated SCD load resistors.

Core Material: Ultra-pure Single Crystal Diamond (SCD) used as the wide bandgap semiconductor platform.
Key Dielectric: Atomic Layer Deposition (ALD) of 15 nm Al₂O₃ served as the gate dielectric and passivation layer, crucial for stabilizing the Two-Dimensional Hole Gas (2DHG).
High Performance: Achieved a maximum saturated drain current (I_DS,sat) of 113.4 mA/mm (L_G = 4 µm).
Switching Efficiency: Demonstrated an outstanding on/off current ratio greater than 10⁹, validating suitability for low-power switching applications.
Logic Function: The integrated inverter circuit achieved a maximum voltage gain of 10.
Methodology Validation: The use of an integrated resistive load element confirms the potential for monolithic integration of diamond logic circuits.

Technical Specifications

The following performance and fabrication metrics were extracted directly from the research paper:

Parameter	Value	Unit	Context
Substrate Material	Single Crystal Diamond (SCD)	N/A	(100) Orientation, 0.5 mm thick
Maximum Output Current (I_DS,sat)	113.4	mA/mm	Measured at V_GS = -6 V
On/Off Current Ratio	> 10⁹	N/A	Ultra-high switching performance
Maximum Transconductance (g_m)	24	mS/mm	Measured at V_GS = -0.2 V
Threshold Voltage (V_TH)	5.2	V	Depletion-mode device operation
Subthreshold Swing (SS)	117	mV/dec	Near-ideal switching efficiency
Maximum Inverter Gain	10	N/A	Achieved with R_D = 136.4 kΩ load
Gate Length (L_G) / Width (W)	4 / 50	µm	MOSFET dimensions
Al₂O₃ Dielectric Thickness	15	nm	Deposited via ALD
ALD Deposition Temperature	300	°C	Used H₂O as the oxidizing agent
H-Plasma Treatment Temperature	800	°C	Required for surface termination

Key Methodologies

The following is an outline of the crucial fabrication steps employed to realize the high-performance H-Diamond MOSFET logic inverter:

Substrate Cleaning: SCD (100) substrates (8.0 mm x 8.0 mm) were cleaned using a solution of HNO₃ and H₂SO₄ at 250 °C for 30 minutes to remove contaminants and non-diamond phases.
Hydrogen Termination: MPCVD was used to subject the substrates to a hydrogen plasma treatment.
- Recipe Parameters: H₂ flow: 500 sccm; CH₄ flow: 1 sccm; Microwave Power: 2 kW; Pressure: 100 mbar.
- Conditions: Substrate temperature maintained at 800 °C for 30 minutes.
2DHG Formation: The H-terminated surface was exposed to air to spontaneously form the stabilizing adsorption layer necessary for the 2DHG (Two-Dimensional Hole Gas) layer.
Ohmic Contact Definition: A 100 nm thick Gold (Au) layer was deposited via electron beam evaporation to serve as the Ohmic source/drain electrodes.
Device Isolation: Low-power oxygen plasma etching was used to achieve device isolation (MESFET structure).
Gate Dielectric Deposition: 15 nm of Al₂O₃ was deposited via Atomic Layer Deposition (ALD) at 300 °C, utilizing H₂O as the oxidizing agent.
Gate Metalization: A 100 nm layer of Aluminum (Al) was deposited via electron beam evaporation to form the gate electrode.
Resistor Integration: Load resistors (R_D) were simultaneously defined on the SCD surface using Au contacts, providing integrated resistive loads of 16.7 kΩ, 69.5 kΩ, and 136.4 kΩ by varying the electrode spacing (20, 80, and 160 µm).

6CCVD Solutions & Capabilities

6CCVD provides the high-quality Single Crystal Diamond required to replicate, scale, and optimize this cutting-edge research in wide bandgap logic circuits. Our bespoke material science capabilities directly address the needs of advanced H-Diamond device fabrication.

Applicable Materials

The foundation of this high-performance inverter is the quality and purity of the SCD substrate.

Material Required: Electronic Grade Single Crystal Diamond (SCD), standard (100) orientation.
6CCVD Advantage: We specialize in growing ultra-pure SCD with extremely low intrinsic nitrogen concentration (controlled to below 1 ppm typically), which is vital for maximizing the stability and mobility of the H-terminated 2DHG layer (carrier mobility < 300 cm²/V·s reported in related literature).
Thickness Control: 6CCVD supplies SCD materials in the required thickness range (0.1 µm to 500 µm), allowing researchers to optimize the thermal management and mechanical stability of the final integrated circuit chips.

Customization Potential

This research utilized specific dimensions and metal stacks. 6CCVD’s internal capabilities enable rapid customization to accelerate R&D cycles.

Paper Requirement	6CCVD Solution & Capability	Benefit to Research
Substrate Size	Custom SCD plates up to 10 mm substrates (and PCD up to 125 mm)	Enables scaling from R&D (8 mm x 8 mm used in paper) to pilot production.
Surface Finish	Polishing standard: Ra < 1 nm (SCD)	Ultra-smooth surfaces are critical for subsequent ALD film quality and optimal 2DHG formation/mobility.
Metalization	Internal deposition capabilities (Au, Pt, Ti, Al, W, Cu, Pd)	Enables rapid testing of alternative Ohmic (Au used) and Gate (Al used) metal stacks for thermal stability or lower contact resistance.
Integrated Resistors	Precision laser cutting and patterning support	Allows complex integration patterns for resistive load elements and sophisticated CMOS/NMOS logic designs on SCD.

Engineering Support

Achieving a stable H-terminated diamond surface and integrating high-quality gate dielectrics (like the ALD Al₂O₃ used here) involves complex material science challenges.

6CCVD’s in-house PhD engineering team specializes in diamond surface termination and dielectric interfaces. We offer consultation on selecting the optimal material specifications and surface preparation methodology for similar Wide Bandgap Logic Circuit or High-Frequency MOSFET projects.
We can assist customers in optimizing their SCD growth recipes or post-growth treatments (like the 800 °C H-plasma step) to ensure stable 2DHG formation, leading to reliable, reproducible device performance.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

Diamond has a wide band gap, high carrier mobility, and high thermal conductivity, thereby possessing great potential applications in high power, and high temperature electronics devices, and also inhigh temperature logic circuit. In this work, we fabricate a hydrogen terminated diamond metal-oxide-semiconductor field effect transistor (MOSFET) by using the atomic layer deposition grown Al2O3 as a gate dielectric and passivation layer. The device has a gate length and width of 4 μm and 50 μm, respectively. The device delivers a maximum output current of about 113.4 mA/mm at VGS of -6 V and an ultra-high on/off ratio of 109. In addition, we fabricate three resistors, respectively, with an interelectrode distance of 20, 80 and 160 μm, corresponding to the resistance value of 16.7, 69.5 and 136.4 kΩ, respectively. The logic inverter is realized by combining the MOSFET with the load resistance, and the characteristics of the logic inverter are demonstrated successfully, which indicates that the diamond MOSFET has great potential applications in future logic circuits.

Tech Support

Original Source

DOI: https://doi.org/10.7498/aps.71.20211447