Noncured Graphene Thermal Interface Materials for High-Power Electronics - Minimizing the Thermal Contact Resistance

At a Glance

Metadata	Details
Publication Date	2021-06-28
Journal	Nanomaterials
Authors	Sriharsha Sudhindra, Fariborz Kargar, Alexander A. Balandin
Institutions	University of California, Riverside
Citations	35
Analysis	Full AI Review Included

Technical Documentation & Analysis: Graphene TIMs for Diamond Electronics

This documentation analyzes the research paper “Noncured Graphene Thermal Interface Materials for High-Power Electronics: Minimizing the Thermal Contact Resistance” to highlight critical material requirements and demonstrate how 6CCVD’s advanced MPCVD diamond substrates provide the necessary foundation for optimizing next-generation thermal management solutions.

Executive Summary

The research confirms that Thermal Contact Resistance ($R_C$) is the dominant bottleneck in high-power electronics thermal management, particularly when using advanced materials like diamond.

Critical Finding: Thermal Contact Resistance ($R_C$) is highly sensitive to surface roughness ($S_q$). An increase in $S_q$ of only $\sim 1$ µm results in an approximate $\times 2$ increase in $R_C$.
Optimal TIM Formulation: Non-curing graphene/FLG TIMs achieve minimum $R_C$ at an optimal filler loading of $\xi \sim 15$ wt% in a silicone oil base.
Thermal Performance: Bulk thermal conductivity ($K_{TIM}$) reached $\sim 4.2$ W m^-1 K^-1 at 40 wt% loading, representing a $24 \times$ enhancement over the base oil.
Relevance to Diamond: The study explicitly targets thermal management for high-power-density electronics implemented with diamond and other wide-band-gap semiconductors, which are often characterized by large interface roughness.
6CCVD Value Proposition: To minimize total thermal resistance ($R_{tot}$), 6CCVD provides ultra-low roughness SCD and PCD substrates (Ra < 1 nm) that eliminate the high $R_C$ penalty associated with rough interfaces, maximizing the efficiency of optimized TIMs.

Technical Specifications

The following hard data points were extracted from the experimental investigation of non-curing graphene TIMs applied to copper plates with varying roughness.

Parameter	Value	Unit	Context
Optimal Graphene Loading ($\xi$)	$\sim 15$	wt%	Minimizes Thermal Contact Resistance ($R_C$)
Maximum Thermal Conductivity ($K_{TIM}$)	$\sim 4.2$	W m^-1 K^-1	Achieved at 40 wt% loading, prior to agglomeration onset
$K_{TIM}$ Enhancement Factor	$24 \times$	Factor	Compared to silicone oil base (0.18 W m^-1 K^-1) at 40 wt%
Roughness Sensitivity	$\times 2$	Factor	Increase in $R_C$ resulting from $\sim 1$ µm increase in $S_q$
Bond Line Thickness (BLT) Range Studied	5 to 35	µm	Range where $R_{tot}$ scales linearly with BLT
Applied Pressure (P)	0.55	MPa	Constant pressure during ASTM D5470-06 testing
Test Temperature	80	°C	Constant temperature for thermal characterization
Areal RMS Roughness ($S_q$) Tested	0.05, 1.2, 2.5, 3.1	µm	Roughness values of polished copper plates
Negligible Copper Plate Resistance	$7.3 \times 10^{-4}$	K cm² W^-1	Thermal resistance of the 1.09 mm thick copper plates

Key Methodologies

The experiment utilized a steady-state thermal testing method (ASTM D5470-06) combined with precise surface metrology to isolate the effect of roughness on thermal contact resistance.

Material Synthesis: Non-curing TIMs were prepared using commercial few-layer graphene (FLG) flakes (xGNP H-25, $\sim 25$ µm lateral dimension) dispersed in a silicone oil (PDMS) base polymer.
Dispersion Process: Acetone was used as a solvent to ensure homogeneous dispersion and prevent filler agglomeration. The mixture was processed using a high-speed shear mixer at 300 rpm for 20 minutes.
Solvent Removal: Acetone was evaporated in an oven at $\sim 70$ °C for 2 hours to ensure the final TIM composition was solvent-free.
Surface Preparation: Copper square plates (1 in $\times$ 1 in, 1.09 mm thick) were polished using 180 grit silicon carbide paper to generate four distinct levels of areal RMS roughness ($S_q$) ranging from 0.05 µm (reference) up to 3.1 µm.
Roughness Metrology: Surface roughness was quantitatively determined using a 3D optical profilometer based on White-Light Interferometry (WLI) with a 50$\times$ Nikon Mirau objective lens.
Thermal Characterization: Measurements were performed using an industrial TIM tester following the ASTM D5470-06 standard under constant conditions (0.55 MPa pressure, 80 °C temperature).
Interface Isolation: Ultra-thin layers of silicone oil were used between the steel tester plates and the copper samples to minimize and fix the contact resistance at the solid-solid interfaces, allowing the isolation of the $R_C$ between the graphene TIM and the copper surfaces.

6CCVD Solutions & Capabilities

The research clearly establishes that the thermal performance of high-power electronics, particularly those based on diamond, is critically limited by interface roughness ($S_q$). Since diamond substrates often exhibit high $S_q$ due to grain structure (PCD) or processing, 6CCVD’s core expertise in producing ultra-smooth MPCVD diamond is the direct solution to this thermal bottleneck.

By providing substrates with $R_a$ values significantly lower than the 0.05 µm baseline used in the study, 6CCVD enables engineers to achieve the lowest possible $R_C$ and maximize the efficiency of optimized graphene TIMs.

Applicable Materials for High-Power Thermal Management

Application Requirement	6CCVD Material Recommendation	Key Specification
Ultra-Low $R_C$ Interface	Optical Grade Single Crystal Diamond (SCD)	$R_a < 1$ nm (Ultra-smooth surface finish)
Large-Area High-Power Modules	Polished Polycrystalline Diamond (PCD)	$R_a < 5$ nm (Inch-size wafers up to 125 mm)
Active Device Layers (SiC/GaN)	High-Purity SCD Substrates	Thicknesses from 0.1 µm up to 500 µm
Integrated Heat Spreading	Thick PCD Substrates	Substrate thickness up to 10 mm

Customization Potential for Advanced Packaging

The study emphasizes that minimizing $R_{tot}$ requires optimizing both the TIM (loading, $K_{TIM}$) and the interface (roughness, $R_C$). 6CCVD provides the necessary material customization to meet these stringent requirements:

Precision Polishing: We guarantee surface roughness $R_a < 1$ nm for SCD and $R_a < 5$ nm for inch-size PCD wafers. This capability directly addresses the paper’s finding that roughness must be minimized to prevent the $\times 2$ penalty in $R_C$.
Custom Dimensions: We offer PCD wafers up to 125 mm in diameter, enabling the scaling required for high-power modules (e.g., IGBT, SiC) where large-area heat sinks are necessary.
Integrated Metalization: For direct bonding and low-resistance electrical contacts, 6CCVD offers in-house metalization services, including deposition of Ti, Pt, Au, Pd, W, and Cu layers, ensuring robust thermal and electrical interfaces between the diamond substrate and the packaging layers (e.g., DBC).

Engineering Support

The non-monotonic dependence of $R_C$ on filler loading ($\xi$) and the extreme sensitivity to $S_q$ demonstrate that material selection and surface preparation are inseparable from TIM optimization. 6CCVD’s in-house PhD team specializes in diamond surface engineering and thermal transport. We offer consultation services to assist researchers and engineers in selecting the optimal diamond material and surface finish required to replicate or extend this research for specific wide-band-gap semiconductor projects.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

We report on experimental investigation of thermal contact resistance, RC, of the noncuring graphene thermal interface materials with the surfaces characterized by different degree of roughness, Sq. It is found that the thermal contact resistance depends on the graphene loading, ξ, non-monotonically, achieving its minimum at the loading fraction of ξ ~~15 wt%. Decreasing the surface roughness by Sq~~1 μm results in approximately the factor of ×2 decrease in the thermal contact resistance for this graphene loading. The obtained dependences of the thermal conductivity, KTIM, thermal contact resistance, RC, and the total thermal resistance of the thermal interface material layer on ξ and Sq can be utilized for optimization of the loading fraction of graphene for specific materials and roughness of the connecting surfaces. Our results are important for the thermal management of high-power-density electronics implemented with diamond and other wide-band-gap semiconductors.

Tech Support

Original Source

DOI: https://doi.org/10.3390/nano11071699

References

2011 - Multigate Transistors as the Future of Classical Metal-Oxide-Semiconductor Field-Effect Transistors [Crossref]
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