The Impact of LCE and PAMDLE Regarding Different CMOS ICs Nodes and High Temperatures

At a Glance

Metadata	Details
Publication Date	2021-01-01
Journal	IEEE Journal of the Electron Devices Society
Authors	Egon Henrique Salerno Galembeck, Christian Renaux, Jacobus W. Swart, Denis Flandre, Salvador Pinillos Gimenez
Institutions	Universidade Estadual de Campinas (UNICAMP), Centro Universitário FEI
Citations	10
Analysis	Full AI Review Included

Technical Documentation & Analysis: High-Temperature CMOS Performance Enhancement

Executive Summary

This analysis focuses on the experimental validation of the Diamond Layout Style (DLS) in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) across various CMOS nodes (180nm Bulk, 1µm SOI) and extreme temperatures (up to 573K). The findings directly support the need for advanced, high-reliability substrate materials, a core offering of 6CCVD.

Performance Boost: DLS MOSFETs (Diamond/Hexagonal gate shape) consistently demonstrated superior analog performance compared to standard Rectangular MOSFETs (RM/RSM).
Key Gains: Average performance gains include 60% for saturation drain current (I_{DS_SAT}) and 51% for transconductance (g_m).
High-Temperature Reliability: The performance-boosting effects (Longitudinal Corner Effect, LCE, and PArallel Connection of MOSFETs with Different Channel Lengths Effect, PAMDLE) remain active and effective up to 573K (300°C).
Technology Independence: The gains provided by DLS are largely independent of the specific CMOS technological node (Bulk vs. SOI).
Analog Circuit Advantage: DLS structures are capable of providing nearly double the normalized amplifier transition frequencies (f_T/(W/L)) compared to RM counterparts, making them ideal for high-gain, high-frequency analog ICs operating in harsh environments.
6CCVD Value Proposition: The demonstrated high-temperature operation (573K) pushes the limits of silicon. 6CCVD’s MPCVD diamond substrates (SCD/PCD) are the ideal material solution for next-generation high-power, high-temperature electronics, offering superior thermal management and electrical isolation necessary to exceed 573K reliability.

Technical Specifications

Parameter	Value	Unit	Context
Operating Temperature Range	300 to 573	K	Full experimental range (27°C to 300°C)
CMOS Technology Nodes Tested	180nm, 1µm	-	Bulk and Silicon-On-Insulator (SOI)
Average I_{DS_SAT} Gain (DLS vs. RM/RSM)	60	%	Saturation drain current gain
Average g_m Gain (DLS vs. RM/RSM)	51	%	Transconductance gain
Minimum I_{DS_SAT} Gain (Bulk, DM/RM)	46	%	Observed across all temperatures
Minimum I_{DS_SAT} Gain (SOI, DSM/RSM)	54	%	Observed across all temperatures
Effective Channel Length Reduction (DM)	23	%	Due to PAMDLE effect (Bulk)
Effective Channel Length Reduction (DSM)	20	%	Due to PAMDLE effect (SOI)
ZTC I_DS Gain (Bulk, DM/RM)	73	%	Zero-Temperature Coefficient Drain Current gain
ZTC I_DS Gain (SOI, DSM/RSM)	81	%	Zero-Temperature Coefficient Drain Current gain
Intrinsic Gain (A_V) Enhancement	~2x	-	DLS provides double the g_m/(W/L) for the same A_V

Key Methodologies

The experimental comparison between Diamond Layout Style (DLS) MOSFETs and Rectangular MOSFETs (RM/RSM) was conducted using the following parameters and techniques:

Device Implementation: Devices were fabricated in two distinct CMOS technological nodes: 180nm Bulk and 1µm Full-Depleted (FD) Silicon-On-Insulator (SOI).
Layout Control: DLS (Diamond/Hexagonal gate) and RM/RSM (Rectangular gate) devices were designed to maintain identical gate area (A_G) and channel width (W) for direct comparison.
Temperature Cycling: Devices were characterized across a wide temperature range from 300K to 573K (27°C to 300°C).
Threshold Voltage (V_TH) Extraction: V_TH was determined using the second-derivative method with a drain-source voltage (V_DS) of 50mV.
Analog Figure of Merit Analysis: Key parameters were analyzed in the saturation region (V_DS > V_GT), including:
- Saturation Drain Current (I_{DS_SAT})
- Transconductance (g_m)
- Output Conductance (g_D)
- Intrinsic Voltage Gain (A_V = g_m/g_D)
- Transconductance-over-Drain Current Ratio (g_m/I_DS)
Zero-Temperature Coefficient (ZTC) Analysis: The ZTC bias point (V_ZTC, I_ZTC) was identified, where I_DS exhibits minimal variation with temperature, confirming stable operation.

6CCVD Solutions & Capabilities

The research demonstrates that advanced layout techniques can push silicon devices to their thermal limits (573K). To replicate this performance reliably, or to extend operation into truly extreme environments (>573K), the underlying substrate must be upgraded. 6CCVD specializes in the materials required for this transition: MPCVD Diamond.

Applicable Materials

The high-temperature application space (analog ICs, high-gain amplifiers) requires substrates with exceptional thermal conductivity and electrical isolation, far exceeding the capabilities of standard silicon or SOI.

6CCVD Material Recommendation	Application Requirement	Key Capability Match
Electronic Grade Single Crystal Diamond (SCD)	Highest thermal dissipation, minimal leakage.	Thermal conductivity > 2000 W/mK. Ideal for Diamond-on-Insulator (DOI) structures or heat spreaders for high-power density ICs.
High Purity Polycrystalline Diamond (PCD)	Large area integration, cost-effective thermal management.	Wafers up to 125mm diameter. Suitable for integrating large-scale CMOS nodes (like the 180nm node tested) in high-reliability packages.
Boron-Doped Diamond (BDD)	High-T sensing and electrochemical applications.	While not directly used in the MOSFET channel here, BDD is critical for integrated high-temperature sensors or electrodes operating alongside the IC.

Customization Potential

The DLS MOSFETs utilize complex, non-standard geometries (hexagonal gates, specific channel lengths L, B, b). 6CCVD’s precision manufacturing capabilities are essential for integrating these advanced designs onto diamond substrates.

Custom Dimensions: 6CCVD provides SCD plates in thicknesses from 0.1µm up to 500µm, and PCD wafers up to 125mm in diameter, supporting both small-scale research and inch-size integration. Substrates up to 10mm thick are available for robust packaging.
Surface Preparation: Achieving the high-quality interface required for subsequent CMOS deposition (as used in the 180nm and 1µm nodes) demands ultra-low roughness. 6CCVD guarantees Ra < 1nm for SCD and Ra < 5nm for inch-size PCD wafers.
Metalization Services: High-temperature electronics often require robust, refractory metal contacts. 6CCVD offers internal, custom metalization capabilities, including Au, Pt, Pd, Ti, W, and Cu, tailored for high-reliability source/drain/gate contacts.

Engineering Support

The physics driving the performance gains—LCE and PAMDLE—are intrinsic to the layout geometry. However, maintaining these gains at high temperatures requires mitigating thermal effects and leakage (I_LEAK).

6CCVD’s in-house PhD team specializes in material science for extreme environments. We can assist researchers and engineers in selecting the optimal diamond material (SCD vs. PCD) and thickness for similar High-Temperature Analog IC projects, ensuring that the superior thermal properties of diamond maximize the reliability and operational ceiling of DLS-based devices.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

This paper describes the influence of Longitudinal Corner Effect (LCE effect) and PArallel Connection of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with Different Channel Lengths Effect (PAMDLE effect) of Diamond (hexagonal gate shape) MOSFET in different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and 1μm- Silicon-On-Insulator, SOI) and in a wide range of high-temperatures (from 300K to 573K). The results have shown (average gains of Diamond MOSFET in relation to standard MOSFET: 60% for saturation drain current, 51% for transconductance, 10% for transconductance-over-drain current ratio etc.) that LCE and PAMDLE effects tend to be similar for CMOS ICs technological nodes used and the different high temperatures. Therefore, we can conclude, for the first time, that LCE and PAMDLE effects are kept active in different CMOS ICs technological nodes and when the Diamond MOSFET is exposed at high temperatures.

Tech Support

Original Source

DOI: https://doi.org/10.1109/jeds.2021.3071399

References

2018 - Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices