Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2021-01-01 |
| Journal | IEEE Access |
| Authors | Fei Wang, Yuan Li, Xiaolei Ma, Jiezhi Chen |
| Institutions | Shandong University |
| Citations | 13 |
| Analysis | Full AI Review Included |
Technical Analysis and Documentation: Defect Engineering in Wide Bandgap Materials for 3D NAND Reliability
Section titled âTechnical Analysis and Documentation: Defect Engineering in Wide Bandgap Materials for 3D NAND ReliabilityâExecutive Summary
Section titled âExecutive SummaryâThis research utilizes first-principles calculations to investigate charge loss mechanisms in Charge-Trap (CT) 3D NAND flash memory, focusing on defects within the $\text{Si}_2\text{N}_2\text{O}$ transition layer. The findings are critical for engineers designing next-generation non-volatile memory devices requiring enhanced reliability and scalability.
- Core Problem: Defects in the $\text{Si}_2\text{N}_2\text{O}$ transition layer (between $\text{Si}_3\text{N}_4$ and $\text{SiO}_2$) induce both lateral and vertical charge loss, severely impacting 3D NAND data retention.
- Shallow Traps Identified: Intrinsic defects like Nitrogen Vacancy ($\text{V}_N$, 0.37 eV), Oxygen Vacancy ($\text{V}_O$, 0.59 eV), and Silicon Interstitial ($\text{Si}_i$, 0.63 eV) act as shallow traps, leading to rapid lateral charge loss via Poole-Frenkel emission.
- Doping Impact: Ti doping, a common strategy, introduces ultra-shallow traps ($\text{Ti}_i$, 0.14 eV), which exacerbate lateral charge loss and promote vertical charge loss by coupling with traps in adjacent layers.
- Mitigation Strategy: Hydrogen (H) passivation is confirmed as an effective method to deepen shallow-trap energy levels (e.g., $\text{V}_N$ deepened to 1.33 eV), thereby suppressing fast charge loss and improving reliability.
- Engineering Implication: The study strongly suggests that precise transition layer treatment and defect control (including H-passivation) are essential for achieving robust reliability in highly scaled CT 3D NAND architectures.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Calculated Band Gap ($\text{E}_g$) | 5.97 | eV | $\text{Si}_2\text{N}_2\text{O}$ crystal (Wide Bandgap Dielectric) |
| Relative Dielectric Constant ($\epsilon_r$) | 6.2 | - | Used in Poole-Frenkel (PF) emission calculations |
| Operating Temperature (T) | 85 | °C | Used in PF emission rate calculations |
| Attempt-to-Escape Frequency ($\text{v}_{PF}$) | $5 \times 10^7$ | $\text{s}^{-1}$ | Used in PF emission rate calculations |
| Intrinsic $\text{V}_N$ Trap Energy ($\text{E}_t$) | 0.37 | eV | Shallow trap, primary cause of lateral charge loss |
| Ti Interstitial ($\text{Ti}_i$) Trap Energy ($\text{E}_t$) | 0.14 | eV | Ultra-shallow trap center in Ti-doped $\text{Si}_2\text{N}_2\text{O}$ |
| H-Passivated $\text{V}_N$ Trap Energy ($\text{E}_t$) | 1.33 | eV | Deepened trap level after H-passivation |
| H-Passivated $\text{V}_O$ Trap Energy ($\text{E}_t$) | 2.24 | eV | Deepened trap level after H-passivation |
| Supercell Size (Atoms) | 360 | - | Used for accurate trap energy level calculation |
| Total Energy Convergence | < $10^{-4}$ | eV | First-principles calculation precision |
| Residual Force | 0.01 | eV/Ă | First-principles calculation precision |
Key Methodologies
Section titled âKey MethodologiesâThe study relied on advanced computational physics techniques to model defect behavior in the wide-bandgap dielectric system:
- Geometric Optimization: Performed using Density Functional Theory (DFT) with the Generalized Gradient Approximation Perdew-Burke-Ernzerhof (GGA-PBE) functional.
- Electronic Properties Calculation: Utilized the screened hybrid functional of Heyd, Scuseria, and Ernzerhof (HSE) with specific parameters ($\alpha = 0.14$, $\omega = 0.2$) to accurately reproduce the $\text{Si}_2\text{N}_2\text{O}$ band gap (5.97 eV).
- Defect Formation Energy: Calculated using the standard formula incorporating chemical potentials ($\mu_i$) and electrostatic potential correction ($\Delta V$) to align reference potentials.
- Charge Loss Rate Modeling: The electron emission rate ($\text{R}_E$) from traps to the conduction band was determined using the Poole-Frenkel (PF) model, simulating performance at $85^\circ \text{C}$.
- Interface Construction: $\text{SiO}_2/\text{Si}_3\text{N}_4$ and $\text{SiO}_2/\text{Si}_2\text{N}_2\text{O}/\text{Si}_3\text{N}_4$ heterojunctions were modeled, with dangling bonds at the interface saturated by hydrogen to eliminate spurious gap defect states.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThe research highlights the critical need for materials with precise defect control, wide bandgaps, and robust thermal managementârequirements where MPCVD Diamond excels. While the paper focuses on silicon oxynitrides, the principles of defect engineering and high-purity dielectrics are directly applicable to advanced diamond-based semiconductor and sensor architectures. 6CCVD provides the necessary materials and engineering support to replicate and extend this research into high-performance domains.
Applicable Materials
Section titled âApplicable Materialsâ| Research Requirement | 6CCVD Material Solution | Technical Rationale |
|---|---|---|
| Wide Bandgap Dielectric/Substrate | Optical Grade Single Crystal Diamond (SCD) | Diamond ($\text{E}_g \sim 5.5 \text{ eV}$) offers a comparable wide bandgap to $\text{Si}_2\text{N}_2\text{O}$ ($\sim 6 \text{ eV}$) but with vastly superior thermal conductivity, making it ideal for high-density 3D stacks where heat dissipation is critical for reliability. |
| Doping and Electrode Studies (Ti, H) | Heavy Boron Doped Diamond (BDD) | BDD films provide a stable, highly conductive electrode material. Researchers can use BDD to study the impact of precise p-type doping on interface charge transfer and defect passivation, analogous to the Ti and H doping studies presented. |
| Large-Scale Integration Substrates | Inch-Size Polycrystalline Diamond (PCD) | PCD wafers (up to 125mm) offer excellent thermal management for large-area semiconductor integration, ensuring device stability under high operating temperatures ($85^\circ \text{C}$ and above) cited in the paper. |
Customization Potential
Section titled âCustomization PotentialâThe complexity of 3D NAND structures, particularly the need for precise transition layers and metal contacts, demands highly customized material solutions. 6CCVD is uniquely positioned to support this advanced research:
- Custom Dimensions: We supply plates and wafers up to 125mm (PCD) and custom-sized SCD, allowing for direct integration into standard semiconductor processing lines and test rigs.
- Thickness Control: 6CCVD offers SCD and PCD films with thickness precision from ultra-thin (0.1 ”m) layers, suitable for studying quantum confinement effects and transition layers, up to robust substrates (10 mm).
- Advanced Metalization: The paper discusses metallic doping (Ti) and the need for reliable contacts. 6CCVD offers in-house metalization services, including Ti, Pt, Au, Pd, W, and Cu deposition, crucial for creating low-resistance ohmic contacts or complex interconnects on diamond surfaces.
- Ultra-Low Roughness Polishing: Our polishing capabilities achieve Ra < 1 nm for SCD and Ra < 5 nm for inch-size PCD, ensuring pristine interfaces necessary for minimizing defect generation and charge trapping, directly addressing the interface reliability issues highlighted in the research.
Engineering Support
Section titled âEngineering Supportâ6CCVDâs in-house PhD team specializes in MPCVD growth and defect physics. We can assist researchers and engineers with material selection and optimization for similar Wide Bandgap Semiconductor and Non-Volatile Memory projects. Our expertise ensures that the diamond material properties (purity, doping concentration, surface termination) are precisely tailored to meet the demanding requirements of advanced device architectures, such as those requiring superior thermal management or specific defect passivation strategies.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si<sub>3</sub>N<sub>4</sub> CT layer and SiO<sub>2</sub> tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss. Here, by first-principles calculations, we present a detailed study on the defects in the transition layer Si<sub>2</sub>N<sub>2</sub>O to comprehend their impacts on charge loss in CT 3D NAND flash memory. It is shown that shallow-trap centers, such as intrinsic nitrogen vacancy (<inline-formula> <tex-math notation=âLaTeXâ>$\text{V}{\mathrm {N}}$ </tex-math></inline-formula>) and interstitial Ti (Ti<inline-formula> <tex-math notation=âLaTeXâ>${\mathrm {i}}$ </tex-math></inline-formula>), can couple with the conduction band of Si<sub>2</sub>N<sub>2</sub>O to lead to lateral charge loss. On the other hand, the N substituting Si atom (<inline-formula> <tex-math notation=âLaTeXâ>$\text{N}{\mathrm {Si}}$ </tex-math></inline-formula>) and Ti substituting Si atom (Ti<inline-formula> <tex-math notation=âLaTeXâ>${\mathrm {Si}}$ </tex-math></inline-formula>) defects in the transition layer can couple through resonance with the trap centers in Si<sub>3</sub>N<sub>4</sub>, leading to vertical charge loss from the CT layer to the transition layer. Our results strongly suggest that appropriate treatment of the transition layer and hydrogen passivation are both important for avoiding charge loss in CT 3D NAND flash memory.