Boosting the MOSFETs Matching by Using Diamond Layout Style
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2020-12-28 |
| Journal | Journal of Integrated Circuits and Systems |
| Authors | Vinicius Vono Peruzzi, Christian Renaux, Denis Flandre, Salvador Pinillos Gimenez |
| Institutions | Centro UniversitĂĄrio FEI, UCLouvain |
| Citations | 1 |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: Diamond Layout Style for Enhanced MOSFET Matching
Section titled âTechnical Documentation & Analysis: Diamond Layout Style for Enhanced MOSFET MatchingâThis documentation analyzes the research paper âBoosting the MOSFETs Matching by Using Diamond Layout Styleâ and connects its findings to 6CCVDâs advanced CVD diamond material solutions, positioning 6CCVD as the essential partner for next-generation high-performance electronics.
Executive Summary
Section titled âExecutive Summaryâ- Core Achievement: The research successfully demonstrates that a novel âDiamond Layout Styleâ (DSnM)âcharacterized by hexagonal/trapezoidal gate geometryâsignificantly improves device matching in Silicon-On-Insulator (SOI) nMOSFETs.
- Performance Gain: The DSnM layout achieved up to 89% reduction in the relative error ($\epsilon_r$) of key parameters (e.g., Ron/1/AR) compared to conventional rectangular layouts (CSnM).
- Mechanism: The enhanced matching is attributed to the synergistic effects of the Longitudinal Corner Effect (LCE) and the Parallel Association of MOSFETs with Different Channel Lengths Effect (PAMDLE).
- Critical Application: Improved device matching is vital for the reliability and performance of high-precision analog and mixed-signal integrated circuits (ICs).
- 6CCVD Value Proposition: While the paper uses the âDiamond Layoutâ on Silicon, 6CCVD provides the actual CVD Diamond material (SCD, PCD, BDD) necessary to implement this superior geometry in Diamond MOSFETs (DMOSFETs) for extreme power and frequency applications, leveraging diamondâs inherent superior properties.
Technical Specifications
Section titled âTechnical SpecificationsâThe following table summarizes the key performance metrics and process parameters extracted from the study, focusing on the maximum device matching improvements achieved by the Diamond Layout Style (DSnM).
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Best Ron Matching Improvement | -89.0 | % | Relative error reduction (DSnM $\alpha$ = 36.9° vs CSnM, LCE + PAMDLE) |
| Best VEA Matching Improvement | -89.9 | % | Relative error reduction (DSnM $\alpha$ = 126.9° vs CSnM, LCE only) |
| Best IDSsat Matching Improvement | -46.2 | % | Relative error reduction (DSnM $\alpha$ = 53.1° vs CSnM, LCE + PAMDLE) |
| Best gmSAT Matching Improvement | -23.7 | % | Relative error reduction (DSnM $\alpha$ = 90° vs CSnM, LCE + PAMDLE) |
| Operating Voltage (VDS) | 1 | V | Saturation Region |
| Operating Voltage (VGS) | 0.4 | V | Saturation/Moderate Inversion |
| Fabrication Process Node | 1 | ”m | CMOS Technology |
| Gate Oxide Thickness | 20 | nm | Standard SOI process parameter |
| Silicon Film Thickness | 180 | nm | Standard SOI process parameter |
| Buried Oxide Thickness | 390 | nm | Standard SOI process parameter |
| Doping Concentration (Source/Drain) | 4x1019 | cm-3 | High doping level |
| Doping Concentration (Channel) | 6.3x1016 | cm-3 | Standard channel doping |
Key Methodologies
Section titled âKey MethodologiesâThe experiment focused on comparative electrical characterization and statistical analysis of devices fabricated using a standard 1 ”m SOI CMOS process.
- Device Fabrication: Both Diamond Layout Style nMOSFETs (DSnMs) and conventional rectangular counterparts (CSnMs) were fabricated on SOI wafers using a 1 ”m CMOS process.
- Geometric Variation: DSnMs were designed with trapezoidal gate geometries, resulting in five distinct $\alpha$ angles tested for statistical analysis: 36.9°, 53.1°, 90°, 126.9°, and 143.1°.
- Statistical Sampling: A large sample size of 360 devices (20 pairs of 9 SOI nMOSFETs for each of the 5 $\alpha$ angles) was analyzed to ensure robust statistical comparison of device matching.
- Parameter Measurement: Key electrical parameters (IDSsat, gmSAT, VEA, Ion, Ron) were measured under saturation (VDS = 1 V, VGS = 0.4 V) and linear (VDS = 50 mV, VGS = 0.4 V) conditions.
- Matching Quantification: Relative error ($\epsilon_r$) was calculated based on the standard deviation and average values of the parameters, normalized by the Aspect Ratio (AR) or Channel Length (L), to quantify the matching improvement due to LCE and PAMDLE effects.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThe research validates a critical design principle: geometric optimization significantly reduces variability. For engineers and scientists seeking to apply this principle to devices requiring extreme performance (high temperature, high power, high frequency), CVD Diamond is the only viable material. 6CCVD provides the necessary materials and fabrication expertise to transition this layout innovation from Silicon to Diamond.
Applicable Materials
Section titled âApplicable MaterialsâTo replicate or extend this research into high-performance Diamond MOSFETs (DMOSFETs) that leverage the DSnM geometry, 6CCVD recommends the following materials:
- Electronic Grade Single Crystal Diamond (SCD):
- Application: Ideal for the active channel layer of DMOSFETs. SCD offers the highest carrier mobility and breakdown field, maximizing the benefits of the optimized DSnM layout for high-frequency analog ICs.
- Specification: SCD plates with thickness ranging from 0.1 ”m to 500 ”m, suitable for epitaxial growth or direct device fabrication.
- Heavy Boron Doped Diamond (BDD):
- Application: Essential for creating highly conductive source and drain regions (p-type doping) required for ohmic contacts in the DSnM structure. BDD ensures low contact resistance, crucial for maximizing current drive (IDSsat).
- Specification: Custom BDD layers available in various doping concentrations and thicknesses.
- Polycrystalline Diamond (PCD) Substrates:
- Application: For large-area power electronics or thermal management layers where the DSnM layout is scaled up. PCD offers superior thermal conductivity for heat dissipation in high-power modules.
- Specification: Wafers available up to 125 mm in diameter, allowing for inch-size device arrays.
Customization Potential
Section titled âCustomization PotentialâThe DSnM layout relies on precise, non-rectangular geometries. 6CCVDâs advanced fabrication capabilities directly support the requirements of this research:
| Requirement from Paper | 6CCVD Customization Capability | Benefit to Researcher |
|---|---|---|
| Complex Geometry (Hexagonal/Trapezoidal) | Custom laser cutting and shaping services. | Enables precise replication of the DSnM $\alpha$ angles (36.9°, 53.1°, etc.) on SCD or PCD wafers. |
| Ohmic/Schottky Contacts | Internal metalization services (Au, Pt, Pd, Ti, W, Cu). | Ensures reliable, low-resistance contacts necessary for the source/drain/gate terminals of the DMOSFET, critical for achieving high IDSsat and low Ron. |
| Surface Quality | Ultra-high precision polishing (Ra < 1 nm for SCD). | Minimizes surface roughness, which is critical for maximizing carrier mobility and reducing variability in the channel region of the DSnM. |
| Scaling | Custom dimensions up to 125 mm (PCD) and substrates up to 10 mm thick. | Supports scaling the DSnM architecture from research prototypes to industrial-scale power modules. |
Engineering Support
Section titled âEngineering Supportâ6CCVDâs in-house PhD team offers authoritative professional support to researchers and engineers. We specialize in the material science required to translate Silicon-based layout optimizations into high-performance diamond devices. We can assist with material selection, doping profiles, and surface preparation necessary for successful Diamond MOSFET (DMOSFET) projects utilizing the DSnM layout.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
This manuscript presents an experimental comparative study between the Metal-Oxide-Semiconductor (MOS) Silicon-On-Insulator (SOI) Field Effect Transistors, n-type, (nMOSFETs) matching, which are implemented with the hexagonal gate shape (Diamond) and standard rectangular ones. The main analog parameters and figures of merit of 360 devices are investigated. The results establish that the Diamond SOI MOSFETs with α angles equal to 90o can boost in more than in average -45.8% with a standard deviation of 20.1% the devices matching in comparison to those found with the typical rectangular SOI MOSFETs, concerning the same gate area and bias conditions. Consequently, the Diamond layout style is an alternative technique to reduce the nMOSFETsâ mismatching, considering the analog SOI Complementary MOS (CMOS) integrated circuits (ICs) applications.