Diamond Field-Effect Transistors With V2O5-Induced Transfer Doping - Scaling to 50-nm Gate Length
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2020-05-06 |
| Journal | IEEE Transactions on Electron Devices |
| Authors | Kevin G. Crawford, James Weil, Pankaj B. Shah, Dmitry Ruzmetov, Mahesh R. Neupane |
| Institutions | DEVCOM Army Research Laboratory |
| Citations | 28 |
| Analysis | Full AI Review Included |
Diamond FETs with V2O5-Induced Transfer Doping: Technical Analysis & 6CCVD Solutions
Section titled âDiamond FETs with V2O5-Induced Transfer Doping: Technical Analysis & 6CCVD SolutionsâExecutive Summary
Section titled âExecutive SummaryâThis research successfully demonstrates the fabrication and measurement of high-performance hydrogen-terminated diamond Field-Effect Transistors (FETs) utilizing Vanadium Pentoxide (V2O5) as a robust surface acceptor for transfer doping.
- Record Performance: Devices achieved a peak drain current of approximately 700 mA/mm and a peak transconductance of 150 mS/mm, setting new benchmarks for diamond Metal Semiconductor FETs (MESFETs).
- Critical Dimension Scaling: Performance gains were directly linked to scaling the gate length ($L_{g}$) down to 50 nm, confirming the potential of diamond for high-frequency (RF) and high-power applications.
- Enhanced Doping Stability: V2O5 encapsulation provided enhanced surface transfer doping, reducing the sheet resistance of the H-terminated diamond surface from 14.2 kΩ/sq to 6.8 kΩ/sq.
- Advanced Fabrication: The process relied on high-resolution e-beam lithography to define nanoscale features and utilized a complex Al/Pt/Au gate metal stack and thermal V2O5 evaporation.
- Material Foundation: The results validate the use of high-quality Single Crystal Diamond (SCD) as the foundational material necessary to support high current density and extreme electric fields.
- Future Focus: Further work is required to integrate high-quality gate dielectrics and hermetic encapsulation to mitigate short-channel effects (DIBL) and ensure long-term device stability.
Technical Specifications
Section titled âTechnical SpecificationsâThe following hard data points were extracted from the device characterization and fabrication process:
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Peak Drain Current (Id) | ~700 | mA/mm | Lg = 50 nm, Vds = -10 V |
| Peak Transconductance (gm) | ~150 | mS/mm | Highest reported value |
| Gate Length (Lg) Range | 50 to 800 | nm | Defined by E-beam lithography |
| Sheet Resistance (Rsheet) (Post-V2O5) | 6.8 | kΩ/sq | Measured via Van der Pauw (VDP) structure |
| Effective Mobility (”eff) | 23.5 | cm2 V-1 s-1 | Estimated value |
| Maximum Gate Capacitance (Cg) | 1.15 | ”F/cm2 | Lg = 400 nm, Vgs = -3 V |
| V2O5 Film Thickness | 40 | nm | Deposited via thermal evaporation |
| V2O5 Anneal Temperature | 350 | °C | In situ pre-deposition anneal |
| Gate Stack Composition | Al/Pt/Au (50/25/45) | nm | Metal Semiconductor FET (MESFET) gate |
| Substrate Material | Single Crystal Diamond (100) | N/A | Element Six source |
Key Methodologies
Section titled âKey MethodologiesâThe fabrication of the V2O5-doped diamond MESFETs involved precise material preparation and nanoscale patterning:
- Substrate Cleaning: Single Crystal Diamond (100) substrate was cleaned using H2SO4:HNO3 solution to remove metallic and organic contaminants.
- Hydrogen Termination: The substrate was hydrogen-terminated in a CVD diamond growth reactor.
- Sacrificial Layer Deposition: 100 nm of Au was thermally evaporated to serve as a sacrificial layer and initial ohmic contact material.
- Device Isolation: Electrical isolation was achieved by patterning and etching the Au sacrificial layer using a KI2 solution, followed by O2 plasma treatment to remove H-termination in exposed areas.
- Probe Pad Metalization: Ti/Au probe pads were deposited to ensure robust contact with the Au ohmic metal.
- Source-Drain Etch: The source-drain region was patterned and etched using a carefully controlled KI2 solution.
- Gate Definition: Gate dimensions (50, 100, 200, 400, 800 nm) were defined using high-resolution E-beam lithography.
- Gate Stack Deposition: The Al/Pt/Au (50/25/45 nm) metal gate stack was deposited.
- V2O5 Encapsulation: A 350 °C in situ anneal was performed, followed by the thermal evaporation of 40 nm V2O5 for transfer doping.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & Capabilitiesâ6CCVD is uniquely positioned to supply the high-quality MPCVD diamond materials and advanced processing services required to replicate, scale, and commercialize the high-performance diamond FETs demonstrated in this research.
Applicable Materials
Section titled âApplicable MaterialsâTo replicate or extend this research, 6CCVD recommends the following materials:
- Optical Grade Single Crystal Diamond (SCD): Required for the highest purity and lowest defect density, essential for achieving the reported high carrier mobility and current density.
- 6CCVD Capability: We supply SCD plates in thicknesses ranging from 0.1 ”m up to 500 ”m, with substrates available up to 10 mm thick, ensuring superior material quality compared to the 4 mm x 4 mm samples used in the study.
- High-Purity Polycrystalline Diamond (PCD): For scaling to larger wafer sizes (e.g., 100 mm or 125 mm) for high-volume manufacturing of power devices where the highest single-crystal purity is not strictly required.
- 6CCVD Capability: PCD plates/wafers are available up to 125 mm in diameter.
Customization Potential
Section titled âCustomization PotentialâThe success of this research hinges on precise material interfaces and complex metal stacks. 6CCVD offers integrated services to meet these exact requirements:
| Research Requirement | 6CCVD Customization Service | Technical Advantage |
|---|---|---|
| Complex Metal Stacks (Al/Pt/Au, Ti/Au) | In-House Metalization: We provide custom deposition of Au, Pt, Pd, Ti, W, and Cu. We can deliver substrates pre-coated with the precise Al/Pt/Au stack (50/25/45 nm) or the Ti/Au probe pads, ready for lithography. | Process Streamlining: Reduces external vendor reliance and ensures optimal adhesion and contact resistance (Rc) for the MESFET structure. |
| Surface Quality (Critical for V2O5 interface) | Ultra-Precision Polishing: Our SCD substrates are polished to achieve a surface roughness (Ra) of < 1 nm. This atomic-level smoothness is critical for minimizing interface traps and maximizing the efficiency of V2O5 transfer doping. | Performance Guarantee: Ensures the highest quality 2-D hole gas (2DHG) channel formation, mitigating the gate leakage observed at 50 nm $L_{g}$. |
| Scaling & Integration (Need for larger wafers) | Custom Dimensions & Laser Cutting: We offer custom dimensions for plates and wafers. For researchers moving toward RF integration, we provide precise laser cutting and shaping services to fit specific device geometries or packaging requirements. | Flexibility: Supports both small-scale R&D (4 mm x 4 mm) and pilot production (inch-size wafers). |
Engineering Support
Section titled âEngineering SupportâThe paper highlights challenges related to gate instability, short channel effects (DIBL), and the need for a high-quality gate dielectric to improve OFF-state performance.
- Dielectric Integration: 6CCVDâs in-house PhD team can assist researchers in selecting and integrating alternative high-k dielectrics (e.g., Al2O3, HfO2) onto H-terminated diamond surfaces, moving beyond the MESFET structure toward more stable MISFET designs, directly addressing the instability issues reported.
- Material Consultation: Our experts specialize in material selection for high-power and radio frequency (RF) applications, ensuring that the chosen SCD or PCD grade meets the specific thermal and electrical demands of next-generation diamond FET projects.
- Global Logistics: We offer global shipping (DDU default, DDP available) to ensure rapid and secure delivery of custom diamond materials worldwide.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
We report on the fabrication and measurement of hydrogen-terminated diamond field-effect transistors (FETs) incorporating V2O5 as a surface acceptor material to induce transfer doping. Comparing a range of gate lengths down to 50 nm, we observe inversely scaling peak output current and transconductance. Devices exhibited a peak drain current of ~700 mA/mm and a peak transconductance of ~150 mS/mm, some of the highest reported thus far for a diamond metal semiconductor FET (MESFET). Reduced sheet resistance of the diamond surface after V2O5 deposition was verified by four probe measurement. These results show great potential for improvement of diamond FET devices through scaling of critical dimensions and adoption of robust transition metal oxides such as V2O5.