Normally-Off Hydrogen-Terminated Diamond Field Effect Transistor With Ferroelectric HfZrOx/Al2O3Gate Dielectrics

At a Glance

Metadata	Details
Publication Date	2020-01-01
Journal	IEEE Access
Authors	Kai Su, Zeyang Ren, Yue Peng, Jinfeng Zhang, Jincheng Zhang
Institutions	Xidian University
Citations	13
Analysis	Full AI Review Included

Technical Documentation & Analysis: Normally-Off H-Diamond FETs

This document analyzes the research detailing the fabrication and performance of a normally-off hydrogen-terminated diamond (H-diamond) Field Effect Transistor (FET) utilizing a ferroelectric $\text{HfZrO}_x/\text{Al}_2\text{O}_3$ stacked gate dielectric. This analysis is tailored to highlight 6CCVD’s capabilities in supplying advanced MPCVD diamond materials for next-generation non-volatile memory and negative capacitance (NC) FET applications.

Executive Summary

The research successfully demonstrates the first H-diamond Metal-Ferroelectric-Insulator-Semiconductor FET (MFISFET) using an Atomic Layer Deposition (ALD)-grown $\text{HfZrO}_x/\text{Al}_2\text{O}_3$ stack, achieving critical normally-off operation.

Novel Device Architecture: Successful integration of ferroelectric $\text{HfZrO}_x/\text{Al}_2\text{O}_3$ gate dielectrics with H-terminated polycrystalline diamond (PCD) via low-temperature ALD ($300^\circ\text{C}$).
Normally-Off Operation: Achieved a completely normally-off behavior in the saturation region ($V_{DS} = -15 \text{ V}$), a highly desirable characteristic for fail-safe logic circuits and high-power applications.
High Performance Metrics: Demonstrated a maximum on/off ratio of $10^9$ and a minimum subthreshold slope (SS) of $58 \text{ mV/decade}$, confirming negative capacitance (NC) characteristics.
Non-Volatile Memory Potential: The device exhibited a wide memory window (MW) ranging from $7.3 \text{ V}$ to $9.2 \text{ V}$, confirming suitability for high-density non-volatile memory integration.
Material Foundation: The device was fabricated on high-quality polycrystalline diamond (PCD), validating the use of large-area MPCVD diamond substrates for advanced electronics.

Technical Specifications

The following hard data points were extracted from the device performance analysis, focusing on the linear region ($V_{DS} = -0.1 \text{ V}$) and saturation region ($V_{DS} = -15 \text{ V}$).

Parameter	Value	Unit	Context
Substrate Material	Polycrystalline Diamond (PCD)	N/A	$10 \text{ mm} \times 10 \text{ mm}$, $250 \text{ µm}$ thick
Gate Dielectric Stack	$\text{HfZrO}_x (16 \text{ nm}) / \text{Al}_2\text{O}_3 (4 \text{ nm})$	nm	Grown by ALD at $300^\circ\text{C}$
Gate Length ($L_G$)	4	µm	MFISFET dimension
Gate Width ($W_G$)	50	µm	MFISFET dimension
Maximum On/Off Ratio	$10^9$	N/A	Linear region ($V_{DS} = -0.1 \text{ V}$)
Minimum SS (Reverse Sweep)	58	$\text{mV/decade}$	Linear region ($V_{DS} = -0.1 \text{ V}$), indicating NC effect
Memory Window (MW)	$7.3 - 9.2$	V	Continuous sweep of 50 cycles
Linear Mobility ($\mu$)	$18.7$	$\text{cm}^2\text{V}^{-1}\text{s}^{-1}$	Calculated at $V_{DS} = -0.1 \text{ V}$
Max Saturation Drain Current	$-51$	$\text{mA/mm}$	Saturation region ($V_{DS} = -15 \text{ V}$)
On-Resistance ($R_{on}$)	$175.1$	$\text{\Omega}\cdot\text{mm}$	Saturation region ($V_{GS} = -7.0 \text{ V}$)
Gate Leakage Current Density ($J_{GS}$)	$< 7.1 \times 10^{-5}$	$\text{A/cm}^2$	At $V_{GS} = -10 \text{ V}$

Key Methodologies

The device fabrication relied heavily on precise MPCVD processing for surface preparation and subsequent ALD for dielectric deposition.

Substrate Preparation: A $10 \text{ mm} \times 10 \text{ mm}$ polycrystalline diamond plate ($250 \text{ µm}$ thick) was used.
Hydrogen Termination (H-Diamond Surface): The sample was treated using hydrogen plasma in an MPCVD chamber for 15 minutes to form the 2DHG channel.
- Gas Flow: $700 \text{ sccm}$
- Pressure: $100 \text{ mbar}$
- Temperature: $850^\circ\text{C}$
- Microwave Power: $2 \text{ kW}$
Ohmic Contact & Protection: $100 \text{ nm}$ thick Au metal film was deposited via electron beam evaporation to form ohmic contacts and protect the H-diamond surface.
Device Isolation: Exposed diamond surface between electrodes was treated with oxygen plasma to form highly resistive oxygen-terminated diamond.
Gate Dielectric Deposition (ALD): $4 \text{ nm}$ $\text{Al}_2\text{O}_3$ and $16 \text{ nm}$ $\text{HfZrO}_x$ films were sequentially deposited at $300^\circ\text{C}$.
- Precursors: Trimethylaluminum (TMA), deionized water ($\text{H}_2\text{O}$), tetrakis-dimethylamido-hafnium (TDMAHf), and tetrakis-dimethylamido-zirconium (TDMAZr).
Gate Metal Deposition: $100 \text{ nm}$ thick Aluminum (Al) was deposited via electron beam evaporation and lifted off to define the gate pattern.

6CCVD Solutions & Capabilities

This research validates the critical role of high-quality MPCVD diamond substrates in developing advanced ferroelectric and negative capacitance FETs. 6CCVD is uniquely positioned to supply the materials necessary to replicate, scale, and advance this research.

Applicable Materials

The paper notes that while PCD was used for its large size and high crystalline quality, Single Crystal Diamond (SCD) is generally more suitable for electronic device fabrication due to the absence of grain boundaries and higher purity.

Research Requirement	6CCVD Recommended Solution	Key Advantage
Current Material (PCD)	Electronic Grade Polycrystalline Diamond (PCD)	Plates up to $125 \text{ mm}$ diameter, ideal for large-area integration and cost-effective scaling of memory arrays.
Next-Gen Material (SCD)	Electronic Grade Single Crystal Diamond (SCD)	Superior carrier mobility and thermal conductivity, eliminating grain boundaries for enhanced device uniformity and maximum performance (e.g., higher $g_m$ and lower $R_{on}$).
Doping Requirement	Boron-Doped Diamond (BDD)	While H-termination creates the 2DHG, BDD substrates are available for researchers exploring alternative p-type channels or complex vertical device architectures.

Customization Potential

6CCVD’s in-house manufacturing capabilities directly address the specific material and processing needs demonstrated in this FET fabrication.

Fabrication Step in Paper	6CCVD Custom Capability	Benefit to Researcher
Substrate Dimensions	Custom plates/wafers up to $125 \text{ mm}$ (PCD) or custom SCD sizes.	Enables scaling from $10 \text{ mm} \times 10 \text{ mm}$ prototypes to inch-size wafers for industrial integration.
Thickness Control	SCD and PCD thickness control from $0.1 \text{ µm}$ to $500 \text{ µm}$.	Allows precise engineering of thermal management and mechanical stability for high-power devices.
Metalization	Internal capability for custom metal stacks (Au, Pt, Pd, Ti, W, Cu).	Direct supply of pre-metalized diamond wafers, streamlining the ohmic contact formation and reducing process steps.
Surface Quality	Polishing to $\text{Ra} < 1 \text{ nm}$ (SCD) and $\text{Ra} < 5 \text{ nm}$ (inch-size PCD).	Essential for minimizing interface defects and maximizing the performance of ultra-thin ALD gate dielectrics like $\text{HfZrO}_x/\text{Al}_2\text{O}_3$.

Engineering Support

The successful demonstration of normally-off H-diamond FETs and Negative Capacitance (NC) effects opens significant avenues for diamond electronics in harsh environments.

Process Optimization: 6CCVD’s in-house PhD team specializes in MPCVD growth parameters, including precise control over the H-termination process ($850^\circ\text{C}$, $2 \text{ kW}$ plasma) required to establish the high-quality 2DHG channel.
Material Selection for NC FETs: We provide expert consultation on selecting the optimal diamond material (SCD vs. PCD) and surface preparation techniques to ensure maximum compatibility with advanced ferroelectric materials like $\text{HfZrO}_x$, crucial for achieving stable sub-$60 \text{ mV/decade}$ SS performance.
Global Logistics: We offer reliable global shipping (DDU default, DDP available) to ensure sensitive electronic-grade diamond substrates reach research facilities worldwide quickly and securely.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

A hydrogen-terminated diamond (H-diamond) Field effect transistor (FET) with a ferroelectric HfZrOx/Al2O3 stacked gate dielectric was demonstrated for the first time. The HfZrOx(16 nm)/Al2O3(4 nm) gate dielectric was grown by atomic layer deposition (ALD) at 300 °C. The bowknot-like capacitance-voltage hysteresis and the transfer characteristic curves in clockwise hysteresis loop directly illustrated the ferroelectricity of the device. A memory window as wide as 7.3-9.2 V, the maximum on/off ratio of 109 and the subthreshold slope (SS) of about 58 mV/decade was measured for the gate voltage sweeping between 10.0 to -10.0 V in the linear region. A completely normally-off behavior was observed in the saturation region because both threshold voltages (Vth ‘s) for forward and reverse sweeping transfer characteristic curves are negative at a drain voltage of -15 V. It is ascribed to that the polarization state of the HfZrOx dielectric along the channel changes from uniform in the linear region to strongly nonuniform in the saturation region. These results hint that HfZrOx/Al2O3/H-diamond FETs provide new possibility of diamond normally-off FETs, negative capacitance FETs and non-volatile memory of high density integration.

Tech Support

Original Source

DOI: https://doi.org/10.1109/access.2020.2968742

References

2018 - Integration and electrical properties of ferroelectric Hf0.5Zr0.5O2 thin film on bulk beta-Ga2O3(-201) substrate for memory applications
2019 - Ferroelectric negative capacitance [Crossref]