A Silicon Cluster Based Single Electron Transistor with Potential Room-Temperature Switching

At a Glance

Metadata	Details
Publication Date	2018-03-01
Journal	Chinese Physics Letters
Authors	Zhanbin Bai, Xiangkai Liu, Zhen Lian, Kangkang Zhang, Guanghou Wang
Institutions	Nanjing University, Rensselaer Polytechnic Institute
Citations	24
Analysis	Full AI Review Included

6CCVD Technical Analysis: Silicon Cluster Single Electron Transistors

Executive Summary

This research demonstrates the successful fabrication and cryogenic characterization of an ultra-small Silicon (Si) atomic cluster-based Single Electron Transistor (SET), highlighting critical metrics for potential room-temperature quantum device operation.

Breakthrough Material: The SET device is based on a single, isolated Si cluster, specifically identified as $\text{Si}_{170 \pm 15}$, with an estimated diameter of 1.8 ± 0.1 nm.
High Charging Energy: A record high charging energy ($\text{E}_{\text{c}}$) of up to 300 meV was achieved, significantly exceeding previous Si quantum dot (QD) reports and suggesting robust stability for potential room-temperature switching applications.
Fabrication Method: The device utilizes a controllable feedback-controlled electromigration process to create a nanometer-scale gold (Au) break junction, capturing the solution-processable Si QD.
Spin Coherence: Spectroscopic measurements reveal a large excited state level spacing (10 meV) and a Lande g-factor of 2.3 ± 0.35, indicating weak electron-electron interaction, which is highly beneficial for maintaining spin coherence time.
Quantum Significance: The SET methodology offers a new spectroscopy technique capable of resolving the electronic and vibrational states of atomic clusters in the meV-order resolution, providing in-depth insight into atomic cluster studies.
6CCVD Value: These findings underscore the need for high-performance, ultra-pure substrates for quantum systems, positioning 6CCVD’s Single Crystal Diamond (SCD) as the ideal platform to enhance spin coherence and thermal stability far beyond conventional silicon.

Technical Specifications

Parameter	Value	Unit	Context
Device Core	$\text{Si}_{170 \pm 15}$ cluster	Atoms	Determined atomic quantity of the captured quantum dot.
QD Diameter	1.8 ± 0.1	nm	Calculated size based on 300 meV charging energy.
Maximum Charging Energy ($\text{E}_{\text{c}}$)	300	meV	Indicates potential for room-temperature operation.
Excited State Level Spacing	10	meV	Allows for individual spin manipulation via magnetic fields.
g Factor (Lande)	2.3 ± 0.35	Dimensionless	Derived from Zeeman splitting measurement slope.
Switching Ratio	> 10	Dimensionless	Confirms robust SET formation and Coulomb blockade.
Electrode Width	70	nm	Patterned Au wire electrodes defined by E-beam lithography.
Break Junction Gap	1 to 2	nm	Estimated physical gap size required for $\text{R} > 1 \text{ M}\Omega$.
Back Gate Dielectric	30	nm	Local $\text{SiO}_{2}$ layer used as the gate insulator.
Measurement Temperature ($\text{T}_{\text{min}}$)	1.6	K	Used for detailed spectroscopic ($\text{dI}/\text{dV}_{\text{sd}}$) measurements.
Magnetic Field Range ($\text{B}$)	-4 to 8	T	Perpendicular field applied for Zeeman effect analysis.
Coupling Parameter ($\alpha$)	$\sim 0.02$	Dimensionless	Coupling between Si QD and $\text{SiO}_{2}$ back gate layer (very weak coupling).

Key Methodologies

The SET fabrication relied on a combination of bottom-up material synthesis, advanced lithography, and precise in-situ junction formation:

Si QD Synthesis: Si QDs were prepared using a nonthermal plasma method, subsequently hydrosilylated with 1-octene, and dissolved in a toluene solution. The mean size of the initial batch was measured via TEM to be 2.7 nm (Std. dev. 0.5 nm).
Electrode Patterning: E-beam lithography (EBL) followed by Electron Beam Evaporation (EBE) was used to deposit narrow gold (Au) electrodes, 70 nm wide, onto a wafer featuring a 30 nm local silicon dioxide ($\text{SiO}_{2}$) back gate layer.
Device Integration: The toluene solution containing the Si QDs was dropped onto the patterned wafer, allowing the QDs to adhere upon drying.
Break Junction Formation: A Keithley 6430 source meter was used to apply a voltage and perform feedback-controlled electromigration on the Au nanowire. This process drives gold atoms to break the wire, forming a nanogap (1 to 2 nm wide) where the $\text{Si}_{170}$ cluster is subsequently captured, resulting in a three-terminal junction.
Cryogenic Transport Measurement: Electrical measurements ($\text{I}{\text{sd}}-\text{V}{\text{sd}}$ and $\text{I}{\text{sd}}-\text{V}{\text{g}}$) were conducted at ultra-low temperatures (1.6 K and 4 K) inside a superconducting magnet system to observe Coulomb blockade and oscillations.
Zeeman Effect Spectroscopy: Detailed differential conductance ($\text{dI}/\text{dV}_{\text{sd}}$) maps were acquired while applying a perpendicular magnetic field ranging from -4 T to 8 T to measure Zeeman splitting and determine the Lande g-factor.

6CCVD Solutions & Capabilities

This research demonstrates a clear need for highly stable, low-noise substrates and precise nanodevice fabrication—areas where 6CCVD’s MPCVD Diamond (SCD/PCD) materials offer crucial competitive advantages for scaling quantum technology.

Applicable Materials

The Si SET utilizes spin-based properties, a field critically dependent on material purity and low decoherence rates. 6CCVD recommends:

Electronic Grade Single Crystal Diamond (SCD): While silicon is used here, high-purity SCD offers the ultimate platform for solid-state spin qubits. Diamond possesses the lowest known spin-orbit coupling and is naturally free of nuclear spin (when ¹²C is used), leading to vastly extended spin coherence times ($\text{T}_{2}$).
Optical Grade SCD Wafers: For applications requiring precise gate control and thermal stability, diamond provides exceptional thermal conductivity (> 2000 W/mK) and superior dielectric properties, stabilizing the device performance under varying power and temperature conditions better than the $\text{SiO}_{2}$ layer used in the current study.
Custom Boron-Doped Diamond (BDD): For hybrid SET architectures, BDD can serve as a robust, conductive substrate or as a highly stable gate electrode material, leveraging diamond’s unparalleled chemical and physical resilience.

Customization Potential

The fabrication of nanogap SETs requires ultra-precise material handling, thin films, and specific electrode architectures. 6CCVD is uniquely equipped to meet these requirements:

Research Requirement	6CCVD Capability	Benefits for Replication/Extension
Thin Film and Wafers	SCD/PCD Thickness up to 500 µm, Substrates up to 10 mm thick. Plates up to 125 mm.	Provides large-area substrates necessary for high-volume E-beam lithography runs.
Metal Electrodes (Au, Ti)	Custom Metalization Services: We deposit Au, Pt, Pd, Ti, W, and Cu via internal capability, allowing researchers to customize source/drain and gate stack contacts (e.g., Ti/Au or $\text{Ti}/\text{Pt}/\text{Au}$).	Eliminates external processing steps, ensuring material purity and adhesion quality on diamond substrates.
High-Fidelity Lithography	Ultra-Smooth Polishing: Achieved surface roughness of $\text{Ra} < 1 \text{ nm}$ for SCD and $\text{Ra} < 5 \text{ nm}$ for PCD.	Guarantees the necessary flatness and quality for nanoscale E-beam lithography (EBL) and the precision required for forming 1-2 nm break junctions.
Custom Dimensions	Precision Laser Cutting: We provide custom cutting and sizing services, ensuring the diamond wafers match the size requirements of existing cryo-system sample holders and chip carriers.	Reduces waste and adapts materials directly to complex experimental setups.

Engineering Support

The work on Si SETs is a critical step in developing next-generation quantum logic and memory devices. 6CCVD’s in-house PhD engineering team provides authoritative support for projects focused on solid-state quantum electronics, including:

Material Selection: Assisting engineers transitioning from traditional silicon/silicon dioxide platforms to advanced diamond substrates for applications requiring maximal spin coherence or high thermal management.
Fabrication Integration: Consulting on the optimal metalization schemes and surface preparation techniques required for integrating nanostructures, like QDs or break junctions, onto diamond substrates.
Global Logistics: Providing global shipping capabilities (DDU default, DDP available) to ensure rapid delivery of custom, high-pvalue diamond materials to research facilities worldwide.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

We demonstrate the fabrication of a single electron transistor device based\non a single ultra-small silicon quantum dot connected to a gold break junction\nwith a nanometer scale separation. The gold break junction is created through a\ncontrollable electromigration process and the individual silicon quantum dot in\nthe junction is determined to be a Si_170 cluster. Differential conductance as\na function of the bias and gate voltage clearly shows the Coulomb diamond which\nconfirms that the transport is dominated by a single silicon quantum dot. It is\nfound that the charging energy can be as large as 300meV, which is a result of\nthe large capacitance of a small silicon quantum dot (1.8 nm). This large\nCoulomb interaction can potentially enable a single electron transistor to work\nat room temperature. The level spacing of the excited state can be as large as\n10 meV, which enables us to manipulate individual spin via an external magnetic\nfield. The resulting Zeeman splitting is measured and the lande factor of 2.3\nis obtained, suggesting relatively weak electron-electron interaction in the\nsilicon quantum dot which is beneficial for spin coherence time.\n

Tech Support

Original Source

DOI: https://doi.org/10.1088/0256-307x/35/3/037301