Diamond FinFET without Hydrogen Termination

At a Glance

Metadata	Details
Publication Date	2018-02-09
Journal	Scientific Reports
Authors	Biqin Huang, Xiwei Bai, Stephen Lam, Kenneth K. Tsang
Institutions	HRL Laboratories (United States)
Citations	28
Analysis	Full AI Review Included

Diamond FinFET without Hydrogen Termination: 6CCVD Technical Analysis

Document Purpose: This analysis translates the key scientific achievements and engineering challenges of the FinFET research paper into actionable technical specifications and material recommendations, showcasing 6CCVD’s capability to supply the specialized MPCVD diamond required for high-performance power and RF electronics development.

Executive Summary

The reported research successfully demonstrates the first diamond FinFET operating via MOS-induced hole accumulation, eliminating the reliance on unstable hydrogen-terminated surfaces. This represents a critical advance for the realization of stable, high-power diamond devices.

Novel Device Architecture: Achieved robust transistor operation using a diamond FinFET structure (100 nm width, 2 µm height) built upon an epitaxially grown Boron-Doped Diamond (BDD) p+/p- bilayer.
Superior Switching Performance: Devices achieved a greater than 3000:1 on/off ratio, successfully proving complete channel pinch-off at zero gate bias without relying on H-termination.
High-Temperature Operation: Demonstrated maximum current density of 30 mA/mm at 150°C, a 35X increase compared to room temperature performance, highlighting viability in high-temperature, high-power environments.
Core Challenge Identified: Device performance, particularly at room temperature, is currently limited by high ohmic contact resistance due to incomplete ionization of boron acceptors.
Material Requirements: Success hinges on highly controlled, high-quality MPCVD growth of heavily boron-doped diamond layers (10¹⁹ cm^-3 range) for source/drain contacts and lightly doped layers (5 x 10¹⁶ cm^-3) for the channel.
Future Application: The diamond FinFET architecture offers enhanced channel control essential for scaling, making it a viable candidate for next-generation RF amplifiers (targeting 100 GHz cutoff) and high-power digital switches.

Technical Specifications

Parameter	Value	Unit	Context
Material Stack	P+/P- Bilayer	-	Epitaxial Boron-Doped Diamond (BDD) on Undoped SCD Substrate
Channel Doping (P-)	5 x 10¹⁶	cm^-3	Lightly doped channel layer (Simulation value)
Contact Doping (P+)	10¹⁹ (Nominal)	cm^-3	Source/Drain regions (Boron concentration)
Fin Width	100	nm	Critical dimension for channel control/pinch-off
P- Layer (Channel) Height	2	µm	Sets the vertical dimension of the fin
Fin Aspect Ratio	~20:1	-	Height to width ratio
Gate Dielectric	45	nm	ALD deposited SiO₂
Max On/Off Ratio	>3000:1	-	Measured transfer characteristic
Max Current Density	30	mA/mm	Achieved at 150°C
RT Current Density	~0.86	mA/mm	Calculated from 838 nA max drain current
Threshold Voltage (V_t)	-2.74	V	Determined by linear extrapolation in saturation region
Ohmic Contact Resistance (RT)	493	Ω*mm	High resistance limiting RT performance
Ohmic Contact Resistance (150°C)	47	Ω*mm	Significant reduction at elevated temperature
Max Breakdown Field (Diamond)	>10	MV/cm	Estimated theoretical limit

Key Methodologies

The FinFET fabrication relies entirely on precise MPCVD growth of the BDD epitaxial structure and advanced nanoscale processing, highlighting the need for high-quality starting materials.

Starting Material Preparation: Undoped, 3 x 3 mm, (100) Single-Crystal Diamond (SCD) substrates were utilized as the foundation for epitaxial growth, acting as a semi-insulating base to reduce leakage.
Bilayer Epitaxial Growth: MPCVD was used to deposit the critical p+/p- bilayer structure. The lighter doped P- layer forms the 2 µm thick channel region, covered by the heavily doped P+ layer for low-resistance contact regions.
Ohmic Contact Definition: The P+ layer was patterned and dry etched to define the ohmic contact areas.
Metalization (Ohmic Contacts): Ti/Pt/Au contact metal was evaporated and annealed at 525 °C in argon gas to ensure a good ohmic interface.
Fin Structure Fabrication: High-resolution E-beam lithography combined with subsequent O₂ plasma dry etching was used to precisely carve the 100-nm wide, 2-µm tall fin channels into the P- layer.
Gate Dielectric Deposition: A 45 nm thick SiO₂ layer was deposited conformally via Atomic Layer Deposition (ALD) at 200 °C to ensure uniform wrapping around the fin sidewalls.
Gate Metalization: A 100 nm thick Aluminum (Al) layer was sputtered and patterned using a lift-off process to achieve the necessary conformal gate wrap required for optimal FinFET channel control.

6CCVD Solutions & Capabilities

This FinFET research directly validates the market need for customized, heavily doped diamond materials and advanced processing services, core specialties of 6CCVD.

Applicable Materials

Replicating or advancing this device requires precise control over the doping profile and crystal quality inherent to MPCVD.

Material Requirement	6CCVD Solution	Technical Rationale
High-Quality Substrate	Optical Grade Single Crystal Diamond (SCD) Substrates	Provides the required low-defect, semi-insulating (100) foundation for epitaxial growth and minimizes substrate leakage.
Active Channel Layer	Light Boron-Doped SCD Epitaxial Wafers (P- type)	Required doping concentration (5 x 10¹⁶ cm^-3) and thickness control (0.1µm to 500µm) for precise channel length engineering.
Low-Resistance Contacts	Heavy Boron-Doped SCD Epitaxial Wafers (P+ type)	Needed for the 10¹⁹ cm^-3 source/drain region. 6CCVD can target doping levels closer to the MIT threshold (~3 x 10²⁰ cm^-3) to maximize activation and minimize contact resistance (the paper’s main limitation).

Customization Potential for FinFET Development

6CCVD’s comprehensive in-house processing capabilities meet the exact demands of nanoscale FinFET fabrication:

Precision Thickness Control: We supply epitaxial layers across the required range (0.1µm to 500µm) for both the P- channel (2 µm used here) and P+ contact layers, ensuring optimal control of the FinFET architecture.
Custom Wafer Dimensions: While the paper used small 3 x 3 mm samples, 6CCVD offers large format PCD plates up to 125 mm. This capability enables future scaling and mass production feasibility studies critical for RF and power applications.
Advanced Metalization Services: The device relied on a custom Ti/Pt/Au stack for ohmic contacts and Al for the gate. 6CCVD provides in-house metalization services, including Au, Pt, Pd, Ti, W, and Cu deposition, customized to the research thermal budget (e.g., 525 °C anneal).
Surface Preparation and Polishing: The fabrication relies on subsequent lithography and etching. 6CCVD ensures the starting SCD wafers have industry-leading smoothness (Ra < 1 nm), crucial for minimizing defects and maximizing the quality of subsequent epitaxial growth and dielectric interfaces.

Engineering Support

The major identified challenge is improving the low carrier activation efficiency at room temperature to overcome high ohmic contact resistance.

6CCVD’s in-house PhD engineering team specializes in BDD growth recipes. We can assist researchers targeting extremely heavy doping concentrations required to achieve the Metal-to-Insulator Transition (MIT) threshold, thereby increasing room temperature carrier mobility and pushing FinFET performance towards the 1 A/mm current density target required for competitive RF and power applications.
We offer consultation on designing complex, multi-layer BDD epitaxial structures suitable for advanced architectures like the p+/p- bilayer used in this research.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

Tech Support

Original Source

DOI: https://doi.org/10.1038/s41598-018-20803-5