Investigation and Comparison of the DIBL Parameter and Thermal Effects of SOD Transistors and SOI Transistors and Improving Them with the Change of Their BOX Thicknesses

At a Glance

Metadata	Details
Publication Date	2018-01-01
Journal	Journal of Electronics Cooling and Thermal Control
Authors	Nooshien Laderian, Arash Daghighi
Institutions	Shahrekord University
Analysis	Full AI Review Included

6CCVD Technical Documentation: High-Power Density CMOS Enabling

Analysis of Silicon-on-Diamond (SOD) Transistor Thermal and Electrical Optimization

Paper Analyzed: Laderian, N. and Daghighi, A. (2018) Investigation and Comparison of the DIBL Parameter and Thermal Effects of SOD Transistors and SOI Transistors and Improving Them with the Change of Their BOX Thicknesses.

Executive Summary

This paper validates the use of ultra-high thermal conductivity MPCVD diamond films as the Buried Oxide (BOX) layer in MOSFETs, demonstrating significant performance enhancements necessary for next-generation, high-power integrated circuits.

Self-Heating Elimination: Replacing standard SiO₂ (k = 1.4 W/K·m) with diamond (k ~ 2000 W/K·m) in the BOX layer reduces the active transistor lattice temperature by over 140 K (from 480 K to 330 K), effectively eliminating the critical self-heating effect (SHE) found in Silicon-on-Insulator (SOI) devices.
High Power Density Enabled: Silicon-on-Diamond (SOD) transistors are shown to sustain power densities over 10 times higher than comparable SOI transistors at the same junction temperature.
Thermal Crosstalk Challenge: Initial implementations using thick buried diamond layers (100 nm) cause uniform heat distribution, leading to increased thermal crosstalk and high off-currents in neighboring transistors.
Optimal Geometry Solution: The proposed optimization—reducing the buried diamond thickness—dramatically improves performance. Reducing the layer from 100 nm down to 10 nm reduces the thermal tail transferred to neighboring devices (improving thermal crosstalk immunity) and substantially improves the Drain Induced Barrier Lowering (DIBL) factor.
Critical Need for CVD Diamond: Replicating or extending this research requires high-purity, uniform, ultra-thin diamond films with precise thickness control in the nanometer range, directly aligning with 6CCVD’s core MPCVD capabilities.

Technical Specifications

Parameter	Value	Unit	Context
Channel Length	22	nm	Standard Transistor Geometry
Diamond Thermal Conductivity (k)	2000	W/K·m	Material substitute for BOX layer (vs. SiO₂)
SiO₂ Thermal Conductivity (k)	1.4	W/K·m	Standard SOI BOX layer
SOI Active T (Max Lattice)	480	K	Worst-case self-heating effect (SHE)
SOD Active T (Max Lattice)	330	K	After diamond BOX substitution (75 K reduction)
Power Density Sustained (SOD)	10x	-	Higher than SOI at identical junction T
Standard Diamond BOX Thickness	100	nm	Initial SOD test thickness
Optimized Diamond BOX Thickness	10	nm	Achieves identical, optimized DIBL as SOI at 10 nm
DIBL (SOI, 100 nm BOX)	76	mV/V	Drain Induced Barrier Lowering
DIBL (SOD, 100 nm BOX)	82	mV/V	Degraded DIBL due to thick diamond layer
DIBL Improvement	8%	-	DIBL of SOD improved by reducing thickness to 10 nm
Neighboring T Reduction (100 nm to 10 nm)	63	K	Thermal tail reduction (447 K down to 384 K)

Key Methodologies

The research utilizes advanced simulation techniques to compare and optimize the thermal and electrical performance of SOI and SOD devices.

Simulation Model: Hydrodynamic Model was used, solving energy conservation equations simultaneously for holes, electrons, and lattice temperature to obtain accurate temperature profiles (Lattice Temperature T_L).
Device Structure: Two structures were compared: Standard SOI MOSFET and SOD MOSFET. Both structures utilized a 22 nm channel length.
Core Material Change: The Buried Insulating Layer (BOX) material was changed from Silicon Dioxide to MPCVD Diamond.
Modeling Inclusions: Simulations included complex physical models such as carrier mobility dependence on doping and lattice temperature, Shockley-Reed-Hall recombination, Auger recombination, and temperature-dependent saturation velocities.
Critical Parameter Sweep: The thickness of the buried diamond layer was systematically varied to determine the optimal structure for mitigating thermal crosstalk and improving DIBL. Tested thicknesses included:
- 100 nm
- 60 nm
- 40 nm
- 10 nm

6CCVD Solutions & Capabilities

The successful implementation of high-performance Silicon-on-Diamond technology hinges on the ability to deposit and process high-quality, ultra-thin diamond films with nanometric precision, a core capability of 6CCVD’s MPCVD manufacturing line.

Applicable Materials

To replicate and extend the performance demonstrated in this research, engineers require MPCVD materials with exceptional purity and high thermal conductivity:

Electronic/Optical Grade Single Crystal Diamond (SCD): Required for applications demanding the highest quality, most uniform thermal properties, and minimal defects, ensuring maximum thermal dissipation efficiency (k ~ 2000 W/K·m).
High-Purity Polycrystalline Diamond (PCD): Applicable for large-area SOD wafers (up to 125mm) where maximizing heat spread across the integrated circuit is paramount for thermal stability.

Customization Potential for SOD Device Fabrication

The key finding of this research is the critical requirement for controlling the diamond BOX layer thickness between 10 nm and 100 nm. 6CCVD is uniquely positioned to supply substrates tailored for this application:

Requirement from Paper	6CCVD Capability	Application Benefit
Ultra-Thin BOX Layers (10 nm to 100 nm)	Precise deposition control from 0.1 µm (100 nm) and advanced post-processing services (etching/polishing).	Enables optimization of DIBL parameter and thermal crosstalk immunity.
Large Scale Integration	Plates/wafers available up to 125mm (PCD).	Supports scaling from R&D (small pieces) to high-volume IC manufacturing.
Surface Quality	Polishing capabilities to achieve Ra < 1nm (SCD) or Ra < 5nm (Inch-size PCD).	Ensures low-defect interfaces necessary for high-mobility channel regions in MOSFET fabrication.
Contact Integration	In-house custom metalization services (Au, Pt, Ti, W, Cu).	Facilitates reliable ohmic contacts and integration with CMOS fabrication processes.
Global Logistics	Global shipping services (DDU default, DDP available).	Ensures rapid delivery of specialized diamond substrates worldwide for time-sensitive R&D projects.

Engineering Support

SOD technology represents a major leap in thermal management for high-power density electronics. 6CCVD’s in-house PhD material scientists and technical engineers specialize in characterizing and tuning MPCVD diamond properties. We provide critical support for:

Determining the optimal material grade (SCD vs. PCD) based on required thermal budget and channel mobility.
Consultation on achieving precise thickness tolerances and surface preparation (polishing) required for advanced High Power Density CMOS projects.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

In this paper, thermal effects and Drain Induced barrier lowering (DIBL) of silicon-on-insulator (SOI) and silicon-on-diamond (SOD) transistors with 22 nm channel lengths using hydrodynamic simulations have been investigated. Thermal conductivity of diamond in contrast to thermal conductivity of silicon dioxide is significantly higher. Hence, the heat transfers faster in silicon-on-diamond transistors. Lattice temperature of SODs is lower than that of similar SOIs. By using SODs in Integrated circuits with the first transistor turning on and active, neighboring transistors will have the same level of heat as the active transistor. As a result, the DIBL factor will be increased; this is an undesired phenomenon in CMOS applications. To resolve this issue, we propose a new method which is the thickness reduction of buried diamond layers inside of transistors. Due to this change, DIBL of active transistor will be improved, the exceeding lattice heat of side transistors will be evacuated through the devices and their temperatures will be deduced in large scale.

Tech Support

Original Source

DOI: https://doi.org/10.4236/jectc.2018.82002