Diamond-powered transistor performs in extreme environments
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2017-08-01 |
| Journal | MRS Bulletin |
| Authors | Rahim Munir |
| Analysis | Full AI Review Included |
Diamond-Powered Transistors for Extreme Environments: Technical & Commercial Analysis
Section titled âDiamond-Powered Transistors for Extreme Environments: Technical & Commercial AnalysisâDocumentation Prepared for 6CCVD (6ccvd.com): Expert MPCVD Diamond Solutions
Executive Summary
Section titled âExecutive SummaryâThis research highlights the successful fabrication of enhancement-mode (E-mode) and depletion-mode (D-mode) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) using epitaxial hydrogenated diamond (H-diamond) grown via Microwave Plasma-Enhanced Chemical Vapor Deposition (MPCVD).
- Core Achievement: Development of diamond-based logic circuits (NOT, NOR) capable of operating in extreme environments (high temperature, high power, high frequency, and radiation).
- Material Specification: A 150 nm thick epitaxial layer of H-diamond was grown specifically for the device architecture.
- Fabrication Method: MPCVD was utilized under specific high-temperature (900-940 °C) and pressure (80 Torr) conditions, followed by complex dielectric stacking (Al2O3) and custom Ti/Au metalization.
- Performance Metric: The NOT logic circuit demonstrated a significant increase in gain maximum, achieving 26.1 (up from 1.2) when the supply voltage was adjusted.
- Technical Roadmap: Current stable operation is limited to <300 °C, with the ultimate target being the reliable, stable function of logic circuits (NOR, NOT, NAND, ring oscillator) at operating temperatures exceeding 500 °C.
- Commercial Potential: These devices are anticipated for commercialization within five years for specialized radiation/space applications and within 10 years for general high-power/high-frequency uses, including the safe dismantling of nuclear reactors.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Diamond Layer Thickness | 150 | nm | Epitaxial H-diamond layer |
| MPCVD Growth Temperature | 900-940 | °C | H-diamond deposition recipe |
| MPCVD Chamber Pressure | 80 | Torr | H-diamond deposition recipe |
| Enhancement Mode Buffer | 4 | nm | Al2O3 (used to reduce lattice mismatch) |
| Depletion Mode Oxide | 30.4 | nm | Al2O3 (Gate Oxide) |
| Metal Stack | Ti/Au | N/A | Deposited via e-beam evaporation |
| NOT Circuit Gain Maximum | 26.1 | N/A | Achieved with VDD = -25.0 V |
| NOT Circuit Supply Voltage (Range) | -5.0 to -25.0 | V | Applied voltage range |
| Current Temperature Limit | <300 | °C | Devices do not perform well above this limit |
| Target Temperature Limit | >500 | °C | Goal for stable logic circuit operation |
Key Methodologies
Section titled âKey MethodologiesâThe core methodology combines precision MPCVD growth of ultra-pure epitaxial diamond with advanced microfabrication techniques for device construction.
- Diamond Growth (MPCVD): A 150 nm thick epitaxial layer of hydrogenated diamond (H-diamond) was grown using Microwave Plasma-Enhanced Chemical Vapor Deposition (MPCVD) at high temperatures (900-940 °C) and a pressure of 80 Torr.
- Dielectric Layer Deposition (E-mode): A thin 4 nm layer of Al2O3 was selected and deposited as a buffer layer to mitigate lattice mismatch effects when coupling the H-diamond with the LaAlO3 substrate for Enhancement-Mode (E-mode) MOSFET architecture.
- Dielectric Layer Deposition (D-mode): A thicker 30.4 nm layer of Al2O3 was deposited directly onto the H-diamond layer for use in Depletion-Mode (D-mode) MOSFET operation.
- Metalization: Device completion involved the deposition of a custom metal stack (Ti/Au) via e-beam evaporation to form the necessary contacts for both E-mode and D-mode configurations.
- Surface Treatment Roadmap: Future work aims to achieve the >500 °C stability target by (a) altering fabrication processes, (b) finding robust ohmic contact metals for H-diamond, (c) using plasma treatment for the H-diamond surface, and (d) modifying oxide insulator deposition conditions.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThis research validates the critical need for highly controlled, ultra-thin epitaxial Single Crystal Diamond (SCD) layers necessary for high-performance power electronics operating in extreme thermal and radiation environments. 6CCVD is uniquely positioned to supply the foundational SCD materials required to replicate and advance this research toward commercial viability.
Applicable Materials
Section titled âApplicable MaterialsâTo achieve the performance demonstrated, researchers require highly uniform, ultra-high quality epitaxial material suitable for electronic devices, followed by precise doping or surface passivation (e.g., hydrogenation).
| Material Required by Paper | Recommended 6CCVD Solution | Rationale and Capability Match |
|---|---|---|
| Epitaxial H-Diamond Layer | Electronic Grade SCD | 6CCVD offers high-purity Single Crystal Diamond (SCD) wafers, essential for epitaxial growth and achieving the necessary high mobility/low defectivity required for high-power FETs. |
| Thin Epitaxial Films | SCD (0.1 ”m - 500 ”m) | The paper uses a 150 nm (0.15 ”m) thick layer. 6CCVD specializes in producing ultra-thin SCD films starting at 0.1 ”m for precise device layering. |
| Future Ohmic Contacts | Polycrystalline Diamond (PCD) / BDD | To address the challenge of finding good ohmic contacts, 6CCVD provides heavily Boron-Doped Diamond (BDD) films, which are often utilized to reduce contact resistance in power electronic applications. |
Customization Potential
Section titled âCustomization PotentialâThe success of this diamond MOSFET relies heavily on precise geometry and tailored interfaces (oxide/metal stacks). 6CCVDâs in-house capabilities directly support the scaling and optimization of these devices:
- Thickness Control: 6CCVD delivers SCD and PCD films with thickness accuracy across the range used in this study (0.1 ”m to 500 ”m), guaranteeing the precise 150 nm thickness needed for optimized channel control.
- Custom Metalization Stacks: The research utilized a Ti/Au stack deposited via e-beam evaporation. 6CCVD offers comprehensive in-house metalization services, including Ti and Au, alongside Pt, Pd, W, and Cu, providing researchers with pre-metallized wafers ready for photolithography.
- Advanced Polishing: Surface quality is paramount for reliable MOSFET gate insulation. 6CCVD guarantees Ra < 1 nm polishing for SCD wafers, ensuring an atomically flat surface critical for minimizing interface defects at the diamond/Al2O3 interface.
- Large Format Capability: For eventual scaling and commercialization, 6CCVD supplies PCD wafers up to 125mm in diameter, enabling mass production of power modules.
Engineering Support
Section titled âEngineering SupportâThe transition from 300 °C to the target 500 °C operation requires intensive material engineering concerning doping, surface termination (H-diamond stability), and interface quality. 6CCVDâs in-house PhD team has deep expertise in MPCVD growth recipes, material selection, and surface treatment protocols necessary to address challenges such as:
- Optimizing diamond growth parameters (T, P, gas flow) to maximize crystal quality and reduce defects.
- Assisting in material selection for similar high-temperature, high-power electronics projects or radiation-hardened space/nuclear applications.
- Consulting on material cleaning, etching, and preparation techniques prior to external oxide insulator deposition.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.