Design of a normally-off diamond JFET for high power integrated applications

At a Glance

Metadata	Details
Publication Date	2017-08-12
Journal	Diamond and Related Materials
Authors	Nazareno Donato, Dario Pagnano, Ettore Napoli, Giorgia Longobardi, F. Udrea
Institutions	University of Cambridge
Citations	18
Analysis	Full AI Review Included

Technical Analysis & Product Recommendation: Normally-Off Diamond JFETs

6CCVD provides the foundational MPCVD diamond materials necessary to realize high-power, normally-off Junction Field Effect Transistors (JFETs) as optimized in this research. The study highlights the critical role of precise doping control and thermal management in achieving superior breakdown voltage (BV) and minimizing specific on-state resistance ($R_{on_spec}$) in enhancement-mode diamond devices.

Executive Summary

This documentation summarizes the optimized theoretical design and simulation of a high-power, normally-off (enhancement mode) p-type diamond JFET, addressing the challenges inherent in Wide Band Gap (WBG) diamond semiconductors.

Core Achievement: Theoretical identification of an optimized diamond JFET structure achieving a 2.7 kV breakdown voltage (BV) at high operating temperature (450 K).
Design Goal: To engineer a normally-off JFET with minimum specific on-state resistance ($R_{on_spec}$) while ensuring operation up to $T_{opt}$ (450 K) and avoiding Punch-Through (PT) breakdown.
Critical Challenge Identified: The incomplete ionization of boron and phosphorus dopants, coupled with temperature dependence, is the primary limiting factor in achieving stable normally-off behavior at elevated temperatures.
Thermal Performance: The optimal design sustains normally-off operation up to 600 K, confirming diamond’s capability for high-temperature power electronics.
Material Necessity: The optimization relies on highly specific, non-uniform doping profiles (N+ gates $8\times10^{19}$ cm^-3; P-channel $5\times10^{16}$ cm^-3) only achievable via high-purity MPCVD Single Crystal Diamond (SCD) layers.
High-Field Capability: The device exhibits a positive temperature coefficient for BV, confirming avalanche phenomenon as the breakdown mechanism, with maximum simulated electric fields exceeding 20 MV/cm.

Technical Specifications

The following parameters define the optimal device structure and its simulated performance targets, derived from TCAD modeling calibrated against experimental data.

Parameter	Value	Unit	Context
Target Breakdown Voltage (BV)	2.0	kV	Design specification
Simulated BV (RT, $L’(d-g)=5$ µm)	2.1	kV	Optimized design performance (300 K)
Simulated BV (450 K, $L’(d-g)=5$ µm)	2.7	kV	Optimized design performance (high temp)
Optimal Operating Temperature ($T_{opt}$)	450	K	Chosen based on minimum resistivity window (450 K - 600 K)
Channel Doping (P-type)	5×10¹⁶	cm^-3	Optimized Boron concentration
Gate Doping (N-type)	8×10¹⁹	cm^-3	Fixed parameter for N+ Gate region
Channel Width ($W_{ch}$)	0.4	µm	Critical dimension for normally-off operation
Channel Length ($L_{ch}$)	1.0	µm	Primary factor regulating Ron_spec and PT breakdown
Drain-Gate Distance ($L’(d-g)$)	5.0	µm	Optimized for BV maximization
Peak Electric Field (Simulated)	>20	MV/cm	Observed at Drain-Gate junction during breakdown
Bulk SCD Breakdown Field	7.7	MV/cm	Reference state-of-the-art property
Boron Ionization Energy ($E_A$)	0.37	eV	P-type acceptor (Incomplete ionization factor)
Phosphorus Ionization Energy ($E_D$)	0.57	eV	N-type donor (Incomplete ionization factor)

Key Methodologies

The optimization utilized an extensive set of two-dimensional TCAD simulations, relying on updated models for mobility, incomplete ionization, and impact ionization, specifically tuned for CVD diamond.

CVD Diamond Modeling: TCAD software utilized models incorporating the incomplete ionization of Boron (acceptor) and Phosphorus (donor) dopants, temperature dependence of saturation velocity, and impact ionization coefficients (Chynoweth model, calibrated to yield 2.1 kV BV at RT).
Fixed Parameters: N-gate doping (8×10¹⁹ cm^-3), Gate-to-Source distance ($L’(s-g)=1$ µm), and Gate width ($W_N=0.7$ µm) were fixed based on known technological limits for diamond JFETs.
Step 1: Optimal Junction Temperature ($T_{opt}$) Selection: Identified 450 K as the optimal maximum operational temperature by analyzing resistivity ($\rho$) minimization without compromising the normally-off state (which becomes difficult above 600 K).
Step 2: Channel Doping Limits ($P_1$ to $P_2$) Establishment: Set technological limits for p-doping between 1×10¹⁵ cm^-3 (lower limit due to control difficulties) and 1×10¹⁷ cm^-3 (upper limit due to breakdown and gate control weakening).
Step 3: Channel Width Limits ($W_1$ to $W_2$) Evaluation: Determined the range for half-channel width ($W_{ch}/2$) to ensure full depletion at zero bias (normally-off) while preventing premature bipolar mode operation.
Step 4: TCAD Parameter Sweep: Simulations varied the three critical parameters—Channel Length ($L_{ch}$), Channel Width ($W_{ch}$), and P-Doping—to target minimum $R_{on_spec}$ and maximized punch-through avoidance (>2 kV).
Step 5: Final Selection and BV Tuning: The structure minimizing $R_{on_spec}$ (0.4 µm $W_{ch}$, 1 µm $L_{ch}$, 5×10¹⁶ cm^-3 doping) was selected. The Drain-to-Gate distance ($L’(d-g)$) was then iteratively increased (optimized to 5 µm) to fulfill the 2 kV BV specification.

6CCVD Solutions & Capabilities

6CCVD provides the high-quality SCD and custom engineering required to fabricate the advanced JFET structure proposed in this research, mitigating the technological obstacles related to precise geometry and doping control.

Applicable Materials & Specifications

The device design requires two distinct, high-quality epitaxial layers: a heavily doped N+ gate region and a moderately doped P-channel region, both necessitating exceptional crystalline perfection for high-voltage integrity.

Device Requirement	6CCVD Material Solution	Relevant Specification
High Voltage/Drift Region	Optical Grade Single Crystal Diamond (SCD)	Thickness up to 500 µm, essential for supporting the 2.7 kV BV and high electric fields.
N+ Gate Layer	Phosphorus-Doped SCD (Custom Doping)	Doping target of 8×10¹⁹ cm^-3. 6CCVD offers high-concentration doping for N-type diamond layers.
P-Channel Layer	Boron-Doped SCD (Custom Doping)	Doping target of 5×10¹⁶ cm^-3, within the technologically feasible range (1×10¹⁵ to 1×10¹⁷ cm^-3).
Surface Finish	Ultra-Smooth Polished SCD Wafers	Ra < 1 nm polish required for high-precision sub-micron lithography and minimizing surface defects which compromise BV.

Customization Potential for Replication

Replicating the optimized JFET design requires micron-scale control over material dimensions and contact deposition, leveraging 6CCVD’s core capabilities:

Precision Doping Control: 6CCVD offers MPCVD diamond growth with highly tailored dopant concentrations (Boron and Boron-Doped Diamond—BDD) across required thicknesses (0.1 µm to 500 µm) to meet the precise $5\times10^{16}$ cm^-3 and $8\times10^{19}$ cm^-3 specifications.
Custom Dimensions: While the device requires small, post-processing features ($W_{ch}=0.4$ µm, $L_{ch}=1$ µm), 6CCVD provides the necessary large-area SCD substrates (up to 125 mm PCD) required for batch processing and integration.
Integrated Metalization: The device utilizes ohmic Source, Drain, and Gate contacts. 6CCVD provides in-house metalization services including refractory metals (Ti, W) and standard contact layers (Pt, Au), crucial for reliable high-temperature operation (up to 450 K).
Wafer Preparation: High-BV designs are highly sensitive to processing defects. 6CCVD ensures high-quality epitaxy and polishing (Ra < 1 nm SCD) essential for reliable operation at electric fields >20 MV/cm.

Engineering Support

The research underscores that high-power diamond device performance is highly sensitive to the complex interplay of incomplete ionization, temperature, and specific geometry ($L_{ch}$, $W_{ch}$).

6CCVD’s in-house PhD team provides specialized engineering consultation to assist clients in selecting optimal material specifications (doping uniformity, compensation ratio, thickness, and surface orientation) for high-temperature Field Effect Transistor (FET) and wide band gap device projects. We support the transfer of optimized TCAD designs into physical MPCVD recipes.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

Tech Support

Original Source

DOI: https://doi.org/10.1016/j.diamond.2017.08.003

References

2010 - Comparison of high voltage and high temperature performances of wide bandgap semiconductors for vertical power devices [Crossref]
2014 - Zr/oxidized diamond interface for high power Schottky diodes [Crossref]
2017 - Durability-enhanced two-dimensional hole gas of CH diamond surface for complementary power inverter applications [Crossref]
2014 - Diamond metal-semiconductor field-effect transistor with breakdown voltage over 1.5kV [Crossref]
2003 - Exceptionally high voltage Schottky diamond diodes and low boron doping [Crossref]
2013 - Electrical characterization of diamond PiN diodes for high voltage applications [Crossref]
2012 - High-voltage vacuum switch with a diamond p-i-n diode using negative electron affinity [Crossref]
2006 - High RF output power for H-terminated diamond FETs [Crossref]