Correlation of nano-scale electrical and topographical mapping of buried nanoscale semiconductor junctions
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2017-07-03 |
| Journal | Lancaster EPrints (Lancaster University) |
| Authors | Ghazi Alsharif, Linda A. HĂ€nel, Alexander Robson, Joachim L. Schultze, Benjamin J. Robinson |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: Conductive Diamond for Nanoscale Semiconductor Characterization
Section titled âTechnical Documentation & Analysis: Conductive Diamond for Nanoscale Semiconductor CharacterizationâThis document analyzes the requirements of the research paper â[1002] Correlation of nano-scale electrical and topographical mapping of buried nanoscale semiconductor junctionsâ and aligns them with the advanced material capabilities offered by 6CCVD.
Executive Summary
Section titled âExecutive SummaryâThe research successfully demonstrates a powerful methodology for characterizing buried semiconductor heterostructures, relying critically on the unique properties of conductive diamond.
- Core Achievement: High spatial resolution (~30 nm) electrical mapping of complex Ge${0.9}$Sn${0.1}$/GeVS multilayer structures.
- Methodology: Combination of Beam-Exit X-section Polishing (BEXP) and Scanning Spreading Resistance Microscopy (SSRM).
- Critical Material: The SSRM setup requires a highly-electrically conductive diamond probe to achieve reliable current mapping under ambient conditions.
- Findings: The technique successfully uncovered variations in conductivity and high defect density layers within the GeVS and GeSn structures following annealing steps.
- Correlation: Electrical data (SSRM) was confirmed by concurrent nanomechanical mapping (Ultrasonic Force Microscopy, UFM).
- 6CCVD Value Proposition: 6CCVD specializes in the production of high-purity, heavy Boron-Doped Diamond (BDD) wafers and plates, which are the ideal precursor material for fabricating the ultra-hard, highly conductive probes required for this advanced nanoscale characterization.
Technical Specifications
Section titled âTechnical SpecificationsâThe following hard data points were extracted from the research paper detailing the experimental parameters and results.
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Material System | Ge${0.9}$Sn${0.1}$ / GeVS / Si | N/A | Multilayer semiconductor heterostructure |
| GeSn Layer Thickness (1) | 100 | nm | MBE grown layer on GeVS |
| GeSn Layer Thickness (2) | 200 | nm | MBE grown layer on GeVS |
| Spatial Resolution (Current Mapping) | ~30 | nm | Achieved via customized SSRM setup |
| BEXP Cross-Section Angle | 5 - 15 | ° | Shallow angle cut for subsurface access |
| Fixed AC Voltage (SSRM) | 1 | Vpp | Used for composite image acquisition |
| DC Offset Range (SSRM) | ±8 | V | Applied during current mapping (Fig 1c) |
| Current Range (Fig 1d) | ±1.5 x 10-5 | A | I-V curve measurement range |
| Conductance Range (Fig 1e) | 0 to 4.0 x 10-6 | Ohms-1 | Measured differential conductance (dI/dV) |
Key Methodologies
Section titled âKey MethodologiesâThe investigation relied on precise material preparation and the use of advanced scanning probe techniques enabled by high-performance diamond tooling.
- Sample Preparation: Ge${0.9}$Sn${0.1}$ layers were grown on gradient Ge virtual substrates (GeVS) via Molecular Beam Epitaxy (MBE) on Si wafers.
- Defect Control: Annealing steps were applied to the GeVS and the total structure to reduce defect density and induce variations in conductivity.
- Cross-Sectioning: High-quality cross sections were formed using Beam-Exit X-section Polishing (BEXP) via Ar-ion cross-sectioning, creating a shallow angle cut (5° to 15°) for subsurface access.
- Electrical Mapping Setup: Scanning Spreading Resistance Microscopy (SSRM) was performed using a conventional SPM system (Bruker Multimode).
- Probe Material: The SSRM utilized a highly-electrically conductive diamond probe coupled with a custom probe-signal pre-amplifier.
- Correlative Analysis: Concurrent nanomechanical mapping was performed using Ultrasonic Force Microscopy (UFM) to confirm electrical variations.
- Environment: All measurements and interpretations of nanoscale electrical transport were conducted under ambient environment conditions.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThe success of this high-resolution electrical mapping technique hinges on the availability of diamond material with exceptional electrical conductivity and mechanical robustness. 6CCVD is uniquely positioned to supply the necessary MPCVD diamond components for replicating and advancing this research.
Applicable Materials for Nanoscale Probes
Section titled âApplicable Materials for Nanoscale ProbesâThe requirement for a âhighly-electrically conductive diamond probeâ necessitates the use of high-quality, heavily doped material.
| 6CCVD Material | Description & Application | Key Advantage for SSRM |
|---|---|---|
| Heavy Boron-Doped Diamond (BDD) | MPCVD grown, optimized for electrical conductivity (p-type). | Ultra-low resistivity (down to 10-4 Ω·cm), ensuring minimal parasitic resistance and maximum signal fidelity during current mapping. |
| Optical Grade SCD | Single Crystal Diamond with high purity and low defect density. | Superior mechanical hardness and wear resistance (Ra < 1 nm polish available), crucial for maintaining the critical ~30 nm tip radius during repeated high-force scanning. |
| PCD Plates (Polycrystalline) | Available in large dimensions (up to 125 mm) for high-volume probe array fabrication. | Cost-effective precursor material for large-scale production of robust, conductive tips. |
Customization Potential for Advanced Characterization
Section titled âCustomization Potential for Advanced Characterizationâ6CCVDâs in-house capabilities directly address the needs of researchers developing customized SPM tools and probes.
| Research Requirement | 6CCVD Customization Service | Benefit to Researcher |
|---|---|---|
| Probe Fabrication Precursor | Custom dimensions and thickness control (SCD/BDD 0.1 ”m to 500 ”m). | Supply of precisely sized plates/wafers for subsequent micro-machining into high-aspect-ratio tips. |
| Integrated Contacts | Custom metalization (Au, Pt, Pd, Ti, W, Cu) on diamond surfaces. | Allows for direct integration of the diamond probe material onto cantilever structures or custom holders with defined ohmic contacts. |
| Surface Finish | Ultra-low roughness polishing (SCD Ra < 1 nm, PCD Ra < 5 nm). | Ensures consistent, low-noise electrical contact with the semiconductor cross-section, critical for high-resolution I-V and SSRM measurements. |
| Substrate Analysis | Large-area substrates up to 125 mm (PCD) or custom SCD sizes. | Provides high-quality diamond substrates for mounting or analyzing large-scale semiconductor wafers. |
Engineering Support
Section titled âEngineering Supportâ6CCVDâs in-house PhD team offers authoritative professional support for material selection in demanding applications:
- Material Optimization: Assistance in selecting the optimal Boron doping level and crystal orientation for specific electrical transport measurements (e.g., maximizing signal-to-noise ratio in SSRM).
- Integration Consultation: Guidance on metalization schemes and surface preparation necessary for integrating diamond components into complex Scanning Probe Microscopy (SPM) systems.
- Global Supply Chain: Reliable global shipping (DDU default, DDP available) ensures timely delivery of custom diamond components to research facilities worldwide.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
In recent years, germanium tin (Ge0.9Sn0.1) group-IV semiconductor materials attracted interest as promising candidates for inclusion in optoelectronic devices. They provide a possible route for realising direct-bandgap semiconductors with increasing Sn content [1], potentially allowing to create LED in a non iii-v semiconductor materials. With the continuing demand for miniaturisation in modern electronic devices, there is a linked demand for new characterisation techniques operating in the nanoscale regime. Here we show that by combining an Ar-ion cross-sectioning technique and a customised scanning probe microscopy (SPM), one can extract and explore the electrical properties of the subsurface Ge0.9Sn0.1 structures with a resolution of ~30 nm. This high spatial resolution current mapping is needed to fully understand the nanoscale mechanisms of electrical transport these complexly structured semiconductor nanostructures and assist in the development of new electronic nano-devices. Beam-Exit X-section Polishing (BEXP) [2], Fig. 1 (a), was used to form high quality cross sections of the layered Ge0.9Sn0.1 samples enabling direct access with scanning spreading resistance microscopy (SSRM) electrical mapping. Our SSRM is based on a conventional SPM system (Bruker Multimode with Nanoscope 4a), with a highly-electrically conductive diamond probe and custom probe-signal pre-amplifier and signal access capabilities. The setup enabled the measurements and interpretation of the nanoscale electrical transport properties and mapping of spreading resistance of the subsurface layers under ambient environment conditions. In this paper we report nanoscale measurements on 100 and 200 nm layer of Ge0.9Sn0.1 on the gradient Ge virtual substrates (GeVS) MBE grown on the Si wafer. We obtained SSRM images, as well as captured (I-V) curves with and without illumination. The annealing of the GeVS allowed low density of the defects immediately under the top GeSnx layer. SSRM allowed to observe that subsequent annealing step of the total structure provide notable variation of the conductivity of the GeSnx layer, as well as to uncover the high defect density layer of the GeVS immediately above Si substrate. These were confirmed by the concurrent nanomechanical mapping via ultrasonic force microscopy (UFM). In conclusion, combination of precise sectioning via BEXP and subsequent SSRM imaging that was demonstrated for the first time in this paper, will be a powerful tool for the investigation of the multilayer semiconductor heterostructures.
Tech Support
Section titled âTech SupportâOriginal Source
Section titled âOriginal Sourceâ- DOI: None