Single carrier trapping and de-trapping in scaled silicon complementary metal-oxide-semiconductor field-effect transistors at low temperatures
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2017-03-24 |
| Journal | Semiconductor Science and Technology |
| Authors | Li Zuo, Muhammad K. Husain, Hiroyuki Yoshimoto, Kazuki Tani, Y. Sasago |
| Institutions | University of Southampton, National Physical Laboratory |
| Citations | 13 |
| Analysis | Full AI Review Included |
Technical Documentation & Analysis: Single Carrier Trapping in Scaled Si CMOSFETs
Section titled âTechnical Documentation & Analysis: Single Carrier Trapping in Scaled Si CMOSFETsâThis document analyzes the research paper âSingle carrier trapping and de-trapping in scaled silicon complementary metal-oxide-semiconductor field-effect transistors at low temperaturesâ (Zuo Li et al 2017 Semicond. Sci. Technol. 32 075001). The analysis focuses on extracting key technical data and leveraging 6CCVDâs MPCVD diamond capabilities to address the challenges and extend the findings into high-performance quantum platforms.
Executive Summary
Section titled âExecutive SummaryâThis research confirms the emergence of quantum mechanical effects in highly scaled, standard Si CMOSFETs at cryogenic temperatures, demonstrating the potential for silicon-based Single Electron Transistors (SETs).
| Feature | Summary | Core Value Proposition |
|---|---|---|
| Observed Phenomena | Single carrier trapping/de-trapping and Coulomb blockade effects (SET characteristics) in 65 nm Si CMOSFETs. | Confirms the feasibility of quantum device operation in scaled semiconductor platforms. |
| Operating Conditions | Quantum effects were only clearly observed at very low temperatures (5 K). | Highlights the thermal limitations of Si for quantum applications, necessitating materials with superior thermal properties. |
| Quantum Dot Mechanism | Quantum dots (QDs) were unintentionally formed by structural disturbances, specifically remote surface roughness caused by poly-Si grain boundaries. | Demonstrates the need for ultra-smooth, high-purity substrates (like SCD) to achieve intentional, stable QD formation and control. |
| Key Dimensions | Estimated QD diameter was 38.5 nm, comparable to the poly-Si grain size (~50 nm). | Requires materials engineering capable of atomic-scale interface control and high-precision fabrication. |
| 6CCVD Advantage | MPCVD Single Crystal Diamond (SCD) offers a superior platform for quantum technology, providing high thermal stability, ultra-low defect density, and the potential for room-temperature operation (e.g., NV centers). | 6CCVD delivers the high-purity, custom-dimension diamond substrates necessary to transition from defect-induced Si quantum effects to stable, engineered diamond quantum devices. |
Technical Specifications
Section titled âTechnical SpecificationsâThe following hard data points were extracted from the experimental results, focusing on device geometry, operating conditions, and derived quantum parameters.
| Parameter | Value | Unit | Context |
|---|---|---|---|
| Technology Node | 65 | nm | Standard CMOS fabrication |
| Measurement Temperature (Low) | 5 | K | Required for clear observation of Coulomb blockade |
| Measurement Temperature (High) | 300 | K | Room temperature baseline |
| Channel Width (W) | 10 | ”m | Chosen to increase probability of observing single carrier effects |
| Channel Length (L) (pMOSFET) | 55 | nm | Scaled device dimension |
| Channel Length (L) (nMOSFET) | 75 | nm | Scaled device dimension |
| Equivalent Oxide Thickness (EOT, tox) | 2.4 | nm | Gate dielectric thickness (SiON) |
| Effective Thickness (teff) | 3.1 | nm | Total capacitive effective thickness (teff = tox + (Δoxtinv / ΔSi)) |
| Quantum Dot Diameter (d) | 38.5 | nm | Estimated for pMOSFET (H3 state) |
| Charging Energy (Ec) (H0) | 7.5 | meV | pMOSFET Coulomb diamond |
| Charging Energy (Ec) (E1) | 4.1 | meV | nMOSFET Coulomb diamond |
| Sub-threshold Slope (nMOSFET, 5 K) | 5.7 | mV/decade | Indicates high gate control and low thermal energy |
| Channel Resistance (5 K) | > 25.8 | kΩ | Necessary condition for observing single-electron effects |
Key Methodologies
Section titled âKey MethodologiesâThe experiment utilized standard semiconductor fabrication and advanced cryogenic electrical characterization techniques to isolate and measure single-carrier phenomena.
- Device Fabrication: MOSFETs were fabricated using a standard 65 nm technology node, featuring doped poly-crystalline silicon (poly-Si) gates and a SiON gate dielectric (EOT 2.4 nm).
- Geometry Selection: A wide channel width (10 ”m) was chosen to maximize the probability of observing local structural disturbances (defects/roughness) acting as quantum dots.
- Cryogenic Measurement: Devices were cooled to 5 K to ensure the thermal energy (kBT) was significantly smaller than the charging energy (Ec), a prerequisite for observing SET characteristics.
- High-Resolution Data Acquisition: Drain current (Id) measurements were obtained by averaging over 105 data points (2 ”s duration) at each bias condition to achieve high sensitivity (detection limit ~1 pA at 5 K).
- 2D Contour Mapping: Two-dimensional contour plots of Id versus Gate Bias (Vg) and Drain Bias (Vd) were generated to visualize the characteristic Coulomb diamonds, confirming single-electron tunneling.
- Mesoscopic Modeling: The standard mesoscopic model was applied to fit the Coulomb diamond borders and extract key parameters, including gate, source, and drain coupling capacitances (Cg, Cs, Cd) and charging energy (Ec).
- Physical Interpretation: Quantum dot formation was physically modeled as potential minima arising from remote surface roughness at the poly-Si/SiON interface, driven by poly-Si grain boundaries.
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & CapabilitiesâThis research demonstrates that quantum effects can be observed in highly scaled Si, but only at extreme cryogenic temperatures (5 K) and relying on unintentional defects (poly-Si grains) to form the quantum dots. 6CCVD offers MPCVD diamond solutions that enable researchers to transition to intentional, stable, and potentially room-temperature quantum platforms.
Applicable Materials
Section titled âApplicable MaterialsâTo replicate or extend this research into a stable, high-performance quantum platform, 6CCVD recommends the following materials:
| 6CCVD Material | Application Focus | Key Advantage over Si |
|---|---|---|
| Electronic Grade SCD | High-mobility SETs, advanced FETs, and high-power electronics. | Ultra-high purity and thermal conductivity (up to 2200 W/m·K), enabling stable operation across a wider temperature range than Si. |
| Optical Grade SCD | Solid-state quantum computing and sensing (NV centers). | Extremely low native defect density, essential for creating and manipulating stable, isolated quantum emitters. |
| Heavy Boron Doped PCD (BDD) | Electrochemical sensing, high-conductivity contacts, and stable electrodes. | High conductivity and chemical inertness, ideal for integration into complex quantum device architectures. |
Customization Potential
Section titled âCustomization PotentialâThe precision required for quantum device fabrication demands highly customized substrates and interfaces. 6CCVDâs in-house capabilities directly address the limitations observed in the Si study (e.g., roughness-induced QDs).
| Requirement from Research | 6CCVD Customization Capability | Technical Specification |
|---|---|---|
| Substrate Size/Geometry | Custom plates and wafers for large-scale integration or specific device layouts. | Plates/wafers up to 125 mm (PCD); Substrates up to 10 mm thick. |
| Interface Quality | Ultra-smooth polishing to eliminate unintentional roughness-induced QDs. | Ra < 1 nm (SCD); Ra < 5 nm (Inch-size PCD). |
| Device Thickness Control | Precise control over active layer thickness for quantum confinement. | SCD/PCD thickness from 0.1 ”m to 500 ”m. |
| Contact Integration | In-house metalization services for reliable source/drain/gate contacts. | Deposition of Au, Pt, Pd, Ti, W, Cu layers. |
Engineering Support
Section titled âEngineering SupportâThe observation of single carrier trapping (HT1, HT2, ET1, ET2) linked to charge traps is a critical reliability issue in scaled Si MOSFETs. Diamond offers a path to mitigate these issues.
- Defect Engineering: 6CCVDâs in-house PhD team specializes in controlling defect density and crystal orientation in MPCVD diamond, which is crucial for minimizing charge traps and maximizing carrier mobilityâa direct improvement over the defect-driven quantum effects observed in the Si study.
- Quantum Platform Design: We provide consultation on material selection and substrate preparation for projects involving Single Electron Transistors (SETs), quantum dots, and Nitrogen-Vacancy (NV) centers, ensuring the material properties are optimized for stable quantum coherence.
- Global Logistics: We ensure reliable, global delivery of custom diamond materials (DDU default, DDP available) to support international research efforts.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
The scaling of Silicon (Si) technology is approaching the physical limit, where various quantum effects such as direct tunnelling and quantum confinement are observed, even at room temperatures. We have measured standard Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (CMOSFETs) with wide and short channels at low temperatures to observe single electron/hole characteristics due to local structural disturbances such as roughness and defects. In fact, we observed Coulomb blockades in sub-threshold regimes of both {\it p}-type and {\it n}-type Si CMOSFETs, showing the presence of quantum dots in the channels. The stability diagrams for the Coulomb blockade were explained by the potential minima due to poly-Si grains. We have also observed sharp current peaks at narrow bias windows at the edges of the Coulomb diamonds, showing resonant tunnelling of single carriers through charge traps.