Charge Trapping Analysis of High Speed Diamond FETs
At a Glance
Section titled âAt a Glanceâ| Metadata | Details |
|---|---|
| Publication Date | 2017-02-06 |
| Journal | MRS Advances |
| Authors | Pankaj B. Shah, James Weil, A. Glen Birdwell, Tony Ivanov |
| Institutions | DEVCOM Army Research Laboratory |
| Citations | 8 |
| Analysis | Full AI Review Included |
Charge Trapping Analysis in High Speed Diamond FETs: Technical Review and 6CCVD Solutions
Section titled âCharge Trapping Analysis in High Speed Diamond FETs: Technical Review and 6CCVD SolutionsâExecutive Summary
Section titled âExecutive SummaryâThis documentation analyzes a critical study focusing on charge carrier trapping mechanisms in high-speed, transfer-doped single crystal diamond (SCD) Field Effect Transistors (FETs). The findings validate diamondâs role as the superior material for next-generation, high-power RF applications, particularly where thermal management limits GaN/III-Nitride devices.
- Material Validation: SCD is confirmed as an optimal material base for high-power FETs due to its unmatched thermal conductivity and high breakdown field.
- Surface Conduction Mechanism: Devices operate via a 2D hole gas formed by atmospheric transfer doping on a hydrogenated diamond surface exhibiting negative electron affinity (NEA).
- Trapping Mechanisms Identified: Two distinct trapping regimes were quantified:
- Deep Traps: Electrons and holes trapped within the Al2O3 gate dielectric, exhibiting slow emission timescales in the range of seconds (leading to slow device turn-on).
- Interface Traps: Fast, acceptor-like traps at the diamond-Al2O3 interface, operating in the microsecond timescale.
- Hydrogenation Optimization: H2 environment annealing (850 °C) resulted in a free hole density of 1.5 x 1013 cm-2, significantly higher than the density achieved via H2 plasma exposure (4.9 x 1012 cm-2).
- Engineering Metric: Conductance-based interface trap analysis provides a robust metric for quantifying surface characteristics necessary to optimize the hydrogenation and transfer doping process.
Technical Specifications
Section titled âTechnical Specificationsâ| Parameter | Value | Unit | Context |
|---|---|---|---|
| Material Base | High Grade SCD | Wafer | Used for high-speed FETs |
| Initial Substrate Size | 3 x 3 | mm | Single Crystal Diamond |
| Hâ Anneal Temperature | 850 | °C | Hydrogenation Method 1 |
| Hâ Anneal Pressure | 700 | Torr | Hydrogenation Method 1 |
| Plasma Hydrogenation Temp | 800 | °C | Hydrogenation Method 2 |
| Gate Dielectric Thickness (AlâOâ) | 160 (16) | Ă (nm) | Electron-beam evaporated AlâOâ |
| AlâOâ Dielectric Constant (k) | 7.2 | - | Estimated from C-V measurements |
| Device Dimensions (LG x W) | 3.5 x 80 | ”m | Typical size used for testing |
| Hâ Anneal Free Hole Density (2D) | 1.5 x 1013 | cm-2 | Resulting density for p-channel |
| Plasma H Free Hole Density (2D) | 4.9 x 1012 | cm-2 | Resulting density for p-channel |
| Hâ Anneal Hole Gas Depth | 16 | nm | Depth of 2D conduction channel |
| Interface Trap Timescale | Microsecond | Range | Diamond - AlâOâ interface traps |
| Deep Trap Timescale | Second | Range | Bulk AlâOâ traps |
| Theoretical Flat-Band Voltage | 0.22 | V | Difference between Al (4.08 eV) and hydrogenated diamond (4.3 eV) work functions |
Key Methodologies
Section titled âKey MethodologiesâThe study relied on high-quality SCD processing and rigorous electrical analysis:
- Substrate Preparation & Cleaning:
- Initial material utilized high grade single crystal diamond (SCD) wafers.
- Two-step chemical cleaning process: 45 minutes in 3:1 HCl:HNO3 at 150 °C, followed by 45 minutes in 3:1 H2SO4:HNO3 at 150 °C. This process oxidized the surface.
- Surface Hydrogenation (2 Techniques):
- Annealing: Wafer annealed for 30 minutes at a substrate temperature of 850 °C in a 700 Torr Hâ atmosphere.
- Plasma Exposure: Wafer exposed to Hâ plasma for 60 minutes at a substrate temperature of 800 °C.
- FET Fabrication (Four-Mask Process):
- Gold deposition/liftoff was used to protect the active region during subsequent processing steps.
- Device Isolation was achieved by exposing areas between devices to a 100 W oxygen plasma for 30 seconds (oxygenation).
- Source and Drain contacts were defined by etching the protective gold layer.
- Gate Stack: 160 Ă of AlâOâ was deposited via electron-beam evaporation, followed by the deposition of an Al/Au gate contact layer.
- Electrical Characterization:
- Measurements performed in the dark using a fully shielded probe station.
- Techniques included Capacitance-Voltage (C-V) analysis (at 1 MHz and variable frequencies) to measure free hole density and trapping.
- Drain Current (ID) transients were analyzed to quantify turn-on speeds and deep-level trapping effects.
- Interface Trap Analysis (G/Ï method) was used to correct for series resistance and calculate trap density (DIT).
6CCVD Solutions & Capabilities
Section titled â6CCVD Solutions & Capabilitiesâ6CCVD provides the high-performance CVD diamond foundation and custom processing required to replicate, optimize, and scale this leading-edge diamond FET research. We specialize in providing materials that minimize interface defects, which directly mitigate the trapping and current collapse phenomena discussed in this paper.
Applicable Materials & Specifications
Section titled âApplicable Materials & Specificationsâ| Research Requirement | 6CCVD Material Recommendation | Technical Benefit |
|---|---|---|
| High Grade SCD (3x3 mm) | Electronic Grade SCD Wafers | Guaranteed high purity and low defectivity essential for stable 2D hole gas formation and high mobility (Figure 6(b)). |
| Thickness Range | SCD (0.1 ”m - 500 ”m) | Flexibility for optimizing thermal sink thickness while maintaining active layer integrity. |
| Large-Area Scalability | PCD Wafers up to 125 mm | Allows transition from lab-scale 3x3 mm samples to commercially viable wafer sizes for industrial production of high-power devices. |
| High Quality Interface | Polishing: Ra < 1 nm (SCD) | Critical for minimizing structural defects at the H-diamond/AlâOâ interface, thereby lowering trap density (DIT) quantified in Figure 4(b). |
| Custom Doping/Functionality | Boron-Doped Diamond (BDD) | Available for researchers exploring bulk doping alternatives or complementary ohmic contact formation strategies. |
Customization Potential
Section titled âCustomization PotentialâThe diamond FET structure described requires precise material interfaces and electrode engineering. 6CCVDâs in-house capabilities meet and exceed the fabrication complexity shown:
- Custom Dimensions: While the paper used small 3x3 mm pieces, 6CCVD offers custom sizing and laser cutting services, ensuring materials fit specific research tooling or commercial dimensions up to 125 mm.
- Integrated Metalization: 6CCVD offers internal thin-film deposition and patterning capabilities (Au, Pt, Pd, Ti, W, Cu). This allows customers to receive diamond substrates already prepared with high-quality ohmic or Schottky contacts (like the Ti/Pt/Au or Al/Au stack mentioned) for immediate device testing, accelerating R&D cycles.
- Surface Preparation Guidance: We provide consultative services regarding optimal surface finish (e.g., polished orientation, roughness) necessary for maximizing the efficiency of post-growth treatments like the Hâ annealing or plasma hydrogenation discussed.
Engineering Support
Section titled âEngineering SupportâDiamondâs advantage rests on high thermal conductivity (critical for mitigating heat generation issues in RF applications, as noted in the Introduction). 6CCVDâs in-house PhD team provides specialized engineering support focused on:
- Material Selection: Assisting researchers in selecting the optimal SCD or PCD grade to balance electrical performance against thermal demands in transfer-doped diamond FET projects.
- Interface Optimization: Consulting on pre- and post-growth processing steps to achieve optimal surface termination, reducing interface trap density (DIT) and enhancing carrier mobility.
- Scale-Up Strategy: Providing technical roadmaps for scaling high-density diamond FET designs from lab prototypes to high-volume manufacturing using large-area PCD.
For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.
View Original Abstract
Abstract Charge carrier trapping in diamond surface conduction field effect transistors (FETs) has been analyzed. For these devices two methods were used to obtain a negative electron affinity diamond surface; either plasma hydrogenation or annealing in an H 2 environment. In both cases the Al 2 O 3 gate dielectric can trap both electrons and holes in deep energy levels with emission timescales of seconds, while the diamond - Al 2 O 3 interface traps exhibit much shorter time scales in the microsecond range. Capacitance-Voltage (CV) analysis indicates that these interface traps exhibit acceptor-like characteristics. Correlation with CV based free hole density measurements indicates that the conductance based interface trap analysis provides a method to quantify surface characteristics that lead to surface conduction in hydrogenated diamond where atmospheric adsorbates provide the acceptor states for transfer doping of the surface.
Tech Support
Section titled âTech SupportâOriginal Source
Section titled âOriginal SourceâReferences
Section titled âReferencesâ- 2014 - Phys. Rev
- 2009 - Appl. Phys. Lett