Analytic modeling of tunnel Field-Effect-Transistors and experimental investigation of GaN High-Electron-Mobility-Transistors

At a Glance

Metadata	Details
Publication Date	2016-01-01
Journal	Munich Personal RePEc Archive (Ludwig Maximilian University of Munich)
Authors	Jianzhi Wu
Analysis	Full AI Review Included

Technical Analysis: GaN HEMTs on MPCVD Diamond Substrates

This documentation analyzes the experimental investigation of GaN High-Electron-Mobility Transistors (HEMTs) fabricated on diamond substrates, focusing on the critical role of diamond in thermal management for high-power and high-frequency applications. The findings directly validate the superior performance of MPCVD diamond as a thermal substrate, aligning perfectly with 6CCVD’s core product offerings.

Executive Summary

Thermal Management Breakthrough: Experimental results confirm that GaN HEMTs fabricated on MPCVD diamond substrates exhibit extraordinary thermal management capability, effectively eliminating self-heating induced current droop observed in GaN-on-Si devices.
Superior Thermal Resistance (Rth): GaN-on-diamond HEMTs achieved a thermal resistance of 41.1 ºC/W, demonstrating a performance improvement of approximately 3.8 times compared to GaN-on-Si HEMTs (156.5 ºC/W).
Scaling Validation: 3D thermal simulations corroborate that diamond substrates provide >3x lower thermal resistance than Si and >2x lower than SiC for comparable HEMT structures, confirming diamond as the optimal material for high-power density devices.
High Output Current Density: A normally-OFF AlGaN/GaN MOS-HEMT utilizing a two-step gate recess technique achieved a maximum output current density of 0.583 A/mm, demonstrating high performance enabled by the robust thermal platform.
Material Requirement: The successful replication and extension of this high-power technology rely on access to high-quality, high-thermal conductivity polycrystalline diamond (PCD) substrates, a specialty of 6CCVD.

Technical Specifications

The following hard data points were extracted primarily from the experimental investigation of GaN HEMTs on diamond (Chapter 8 and 9).

Parameter	Value	Unit	Context
Thermal Resistance (Rth) - Diamond	41.1	ºC/W	Extracted from GaN-on-diamond HEMT
Thermal Resistance (Rth) - Silicon	156.5	ºC/W	Extracted from GaN-on-Si HEMT (Control)
Thermal Conductivity (Bulk Diamond)	>1500	W/m-K	Reference value for high-quality diamond
Thermal Conductivity (SiC Reference)	~350	W/m-K	Reference value for SiC substrate
Diamond Substrate Thickness	~95	µm	Thickness of polycrystalline diamond layer
GaN Buffer Layer Thickness	~800	nm	GaN buffer layer on diamond
Gate Length (Lg)	2	µm	HEMT device dimension
Gate Width (W)	50	µm	HEMT device dimension
Maximum Output Current Density (Imax)	0.583	A/mm	Gate recessed MOS-HEMT (Fig. 9.2 inset)
Threshold Voltage (Vth) - Diamond	-3.0	V	GaN-on-diamond HEMT (Depletion Mode)
Threshold Voltage (Vth) - Recessed	+1.0	V	Normally-OFF MOS-HEMT (Enhancement Mode)
Field Effect Mobility (Diamond)	833	cm²/(V·s)	Extracted from I-V characteristics

Key Methodologies

The experimental investigation of GaN HEMTs on diamond utilized advanced fabrication and characterization techniques:

Epitaxial Structure Preparation: GaN epitaxial layers were grown on a test structure, followed by the growth of polycrystalline diamond on the backside. A low thermal conductivity transition layer was intentionally removed to minimize thermal resistance between the GaN epilayer and the diamond substrate.
Mesa Isolation: Achieved using an Ar/Cl₂/BCl₃ plasma-based Reactive-Ion Etching (RIE) system.
Ohmic Contact Formation: Ti/Al/Ti/Au metal stack was deposited via e-beam evaporation, followed by 30s Rapid Thermal Annealing (RTA) at 850 °C in N₂ ambient.
Gate Recess (for E-Mode): A two-step process was used: (1) ICP BCl₃/Cl₂ plasma etching to define the recess region, followed by (2) wet chemical etching (diluted HCl and NH₄OH) to smooth the surface and remove damaged residues.
Gate Dielectric and Metal: A 20-nm-thick ALD Al₂O₃ layer was deposited as the gate dielectric, followed by Ni/Au e-beam evaporation for the Schottky gate.
Thermal Resistance Extraction: Thermal resistance (Rth) was quantitatively extracted using temperature-dependent Direct-Current (DC) Current-Voltage (I-V) measurements, analyzing the self-heating induced current droop (ΔI_sat).
Thermal Simulation Validation: Results were corroborated using 3D thermal simulations (COMSOL) to model the temperature profile and effective thermal resistance across the GaN/adhesion layer/diamond structure.

6CCVD Solutions & Capabilities

The research highlights the critical need for high-quality, high-thermal conductivity diamond substrates to unlock the full potential of GaN HEMTs for high-power applications. 6CCVD is uniquely positioned to supply the materials required to replicate and advance this research.

Applicable Materials

To achieve the superior thermal performance demonstrated in this study, researchers require high-quality polycrystalline diamond (PCD) substrates.

Polycrystalline Diamond (PCD): 6CCVD offers high-purity, high-thermal conductivity MPCVD PCD wafers, ideal for thermal management in GaN HEMT applications. Our PCD material ensures the low thermal resistance (Rth < 50 ºC/W) necessary to eliminate current droop.
Single Crystal Diamond (SCD): For future research requiring ultra-low surface roughness (Ra < 1nm) or specific crystallographic orientations, 6CCVD supplies high-quality SCD plates.
Boron-Doped Diamond (BDD): While not the primary focus of the thermal substrate, BDD material is available for researchers exploring diamond-based active devices or highly conductive contacts.

Customization Potential

The fabrication process detailed in the dissertation requires precise material dimensions and specific metal stacks, capabilities that 6CCVD provides as standard services:

Research Requirement	6CCVD Capability	Benefit to Researcher
Substrate Dimensions	PCD plates/wafers up to 125mm (5 inches) in diameter.	Enables scaling beyond the 4-inch wafer size mentioned, facilitating mass manufacturability studies.
Substrate Thickness	PCD thickness ranging from 0.1 µm to 500 µm, and substrates up to 10 mm.	Easily meets the 95 µm thickness requirement and allows for optimization studies across a wide range of thermal budgets.
Metalization Stacks	In-house capability for deposition of Au, Pt, Pd, Ti, W, Cu.	Supports the complex ohmic (Ti/Al/Ti/Au) and Schottky (Ni/Au) contact schemes used in the HEMT fabrication.
Surface Finish	Polishing capability to achieve Ra < 5nm on inch-size PCD.	Ensures optimal interface quality for subsequent GaN epitaxial growth and device processing.

Engineering Support

6CCVD’s in-house team of PhD material scientists and engineers specializes in optimizing MPCVD diamond properties for advanced electronic applications. We can assist researchers and engineers working on similar GaN HEMT thermal management projects by:

Consulting on the optimal PCD grade and thickness required to meet specific thermal budget targets (e.g., Rth < 40 ºC/W).
Providing customized metalization schemes tailored for specific III-V semiconductor interfaces (e.g., AlGaN/GaN).
Offering global shipping (DDU default, DDP available) to ensure rapid delivery of custom diamond materials worldwide.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

High density and lower power drive the aggressive scaling down of CMOS transistors. Yet, the scaling of Si bulk MOSFETs are approaching physical limits, suffering from poor electrostatic control due to short channel effects, gate leakage current caused by gate oxide tunneling, and most importantly the non-scaled supply voltage imposed by thermionic emission limitation. Tunnel FETs (TFETs) based on band-to-band tunneling current injection mechanism, have emerged as promising candidates to deliver steep turn-off slopes, thus enables a sharp reduction of supply voltage to below 0.5 V. This dissertation is primarily devoted to develop an accurate analytic model for TFETs with a double-gate structure, providing physical insights to the design principles. At the core of the model is a gate-controlled channel potential that satisfies the source and drain boundary conditions. The potential is of an exponential profile with a characteristic scale length given by the device thickness. Both the source-to-channel tunneling and source-to-drain tunneling are developed and included in the model. It has been verified by numerical simulations for a wide range of bandgaps and channel lengths. Also incorporated in the model are the short-channel effect, source doping effect, ambipolar effect, and de-bias of gate voltage by channel charge. Based on these, the guidelines for scaling TFETs to sub-10-nm channel lengths are brought forth. The model is continuous, physical and predictive in the sense that there is no need for ad hoc fitting parameters. For high-power and high-frequency applications, GaN high-electron-mobility-transistors (HEMTs) stand out as promising candidate devices for achieving high breakdown voltage, high output current and high transconductance characteristics. Yet, the performance of GaN HEMTs suffers from mobility degradation due to poor thermal dissipation of conventional epitaxial substrates. This dissertation also experimentally demonstrates the GaN HEMTs fabricated on diamond substrate with extraordinary thermal management capability. The self-heating induced current droop is effectively absent in the saturated Ids-Vds characteristics of the resulting devices, thus paving the way for enhancing the energy conversion efficiency.

Tech Support

Original Source

DOI: None