Field-Induced Crystalline-to-Amorphous Phase Transformation on the Si Nano-Apex and the Achieving of Highly Reliable Si Nano-Cathodes

At a Glance

Metadata	Details
Publication Date	2015-05-21
Journal	Scientific Reports
Authors	Yifeng Huang, Zexiang Deng, Weiliang Wang, Chaolun Liang, Juncong She
Institutions	SYSU-CMU International Joint Research Institute, Key Laboratory of Guangdong Province
Citations	37
Analysis	Full AI Review Included

6CCVD Technical Analysis: High-Reliability Si Nano-Cathodes using Diamond Coating

Executive Summary

This research investigates the reliability challenge in Si nano-cathodes for vacuum channel transistors (VCTs), specifically detailing the mechanism of field-induced crystalline-to-amorphous phase transformation (amorphization) and presenting a diamond-based solution.

Failure Mechanism Identified: Si nano-tip apexes deform into an amorphous “nano-whisker” structure under low macroscopic electric fields (0.6-1.65 V/nm) and ultra-low emission currents (~1 pA).
Physical Basis: The deformation is caused by a strong electrostatic force acting on highly concentrated electron charge (Mulliken charges) accumulated at the arsenic-rich Si tip surface, leading to Si-Si bond elongation and atomic migration.
Dopant Accumulation: Thermal sharpening (oxidation at 1000°C) causes arsenic dopant accumulation at the tip apex, increasing inner stress and reducing the critical field required for amorphization (simulated Ecrit reduced from 0.110 V/nm to 0.063 V/nm).
Diamond Solution: Highly reliable Si nano-cathodes were achieved by coating the apex with a 3 nm thick Diamond-Like Carbon (DLC) film.
DLC Functionality: DLC enhances field emission via “quasi-tunneling” across the Si/DLC Schottky barrier (~0.9 eV) while providing mechanical reinforcement due to the significantly stronger C-C bonds (85 kcal/mol) compared to Si-Si bonds (54 kcal/mol).
Application Significance: The findings are crucial for developing highly reliable Si-based nano-scale vacuum channel transistors (VCTs) and future Si nano-electronic devices requiring narrow separation gaps.

Technical Specifications

Parameter	Value	Unit	Context / Condition
Cathode Substrate	Heavily Arsenic-Doped Si	~10¹⁹/cm³	Mono-crystalline Si (0.005 Ω cm)
Initial Tip Apex Radius	2-5	nm	Measured before field emission test
Tip Height	1.0	µm	Typical geometry
Field-Induced Deformation Start	0.6 - 1.65	V/nm	Macroscopic electric field, ultra-low current
Ultra-Low Emission Current	1 - 10	pA	Observed during deformation onset
Vacuum Level (Testing)	~1.0 x 10^-4	Pa	Achieved using SEM system
Critical Deformation Field (Simulated Si₅₄)	30	V/nm	Theoretical calculation for Si₅₄H₂₂O₁₅ cluster
Critical Deformation Field (Simulated As-doped Si₅₂)	0.063 - 0.110	V/nm	Non-linear decrease with As concentration
Thermal Sharpening Conditions	1000	°C	7 hours oxidation, induces As accumulation
Si-Si Bond Energy	54	kcal/mol	Standard Si covalent bond strength
C-C Bond Energy (DLC)	85	kcal/mol	Used for structural reinforcement
DLC Film Thickness	3	nm	Used for reliable coating, sp³ content ~80%
DLC Optical Band Gap	~1.55	eV	Material property
Si Band Gap	~1.2	eV	Material property
Si/DLC Schottky Barrier Height	~0.9	eV	Formed due to accumulated As dopant
Max Current (Uncoated Si, Unstable)	Several	nA	Breakdown occurs near 0.9-1.0 V/nm
Max Current (DLC Coated Si, Stable)	Up to 128.8	nA	High stability and superior emission performance

Key Methodologies

The highly reliable Si nano-cathodes were fabricated and characterized using a multi-step process integrating standard silicon processing techniques, specialized diamond coating, and advanced analytical methods.

Si Substrate Preparation:
- Material: Mono-crystalline, heavily arsenic-doped Si substrate (~10¹⁹/cm³).
- Purpose: High conductivity for efficient field electron emission.
Si Nano-Tip Array Fabrication (Top-Down Procedure):
- Patterning: Electron Beam Lithography used to define 1 µm diameter dot patterns (AR-N 7520 resist).
- Etching: Patterns transferred into 450 nm thick SiO₂ layer, followed by Si anisotropic etch using an Inductively Coupled Plasma (ICP) etching system with SF₆-based etchant.
Thermal Sharpening and Dopant Segregation:
- Oxidation: Tips sharpened via thermal oxidation at 1000 °C for 7 hours.
- Result: This process intentionally causes the segregation and diffusion of arsenic dopants, forming an arsenic-rich apex, which increases inner stress and facilitates amorphization.
- Cleanup: Oxide removed using hydrofluoric acid (HF). Final tip height typically 1 µm.
Diamond-Like Carbon (DLC) Coating:
- Deposition Method: Filtered Cathodic Vacuum Arc Deposition System.
- Parameters: Thin film thickness of 3 nm with an sp³ content of ~80%.
- Purpose: To enhance emission (quasi-tunneling) and mechanically reinforce the Si tip structure against deformation.
Field Emission Testing:
- Setup: Performed at room temperature in a Scanning Electron Microscope (SEM) system (~1.0 x 10^-4 Pa vacuum).
- Probe: A fine tungsten micro-tip acted as the anode, moved by a piezo-driven nano-motor.
- Separation Gaps: Tests conducted at 50 nm, 100 nm, and 500 nm cathode-to-anode separations.
Structural and Elemental Analysis:
- Techniques: TEM (Transmission Electron Microscope), SAED (Selected Area Electron Diffraction), EDX (Energy-Dispersive X-ray Spectroscopy), and EELS (Electron Energy Loss Spectroscopy).
- Purpose: Confirmation of amorphous phase transformation, whisker composition (Si, O, C ratio), and arsenic dopant concentration profiles.
Theoretical Modeling:
- Calculations: First-Principle calculations based on Density Functional Theory (DFT) using DMol³ code.
- Modeling: Used spheroidal atomic clusters (Si₅₄H₂₂O₁₅ and Si₅₂) to model deformation induced by electrostatic forces (Mulliken charges) and the effect of arsenic doping on the critical deformation field.

6CCVD Solutions & Capabilities: Diamond for High-Reliability Nano-Electronics

This research highlights the superior stability and emission properties provided by a carbon coating (DLC) in high-stress nano-scale field emission applications. 6CCVD, as an expert in high-purity MPCVD diamond, offers materials and engineering services that can surpass the performance demonstrated by the DLC thin films used in this study, providing intrinsically robust and highly conductive cathode solutions.

Applicable Materials

The ideal replacement for or enhancement to the DLC/Si structure is high-quality, conductive Single Crystal Diamond (SCD) or Polycrystalline Diamond (PCD).

6CCVD Material	Application Suitability	Key Advantages over DLC/Si
Boron-Doped Diamond (BDD) Thin Films (SCD/PCD)	Highly Recommended. Perfect for robust, conductive field emitters and electrodes.	Intrinsically conductive material (p-type), requiring no extrinsic dopant accumulation (like Arsenic in Si) to achieve high electron density. Excellent mechanical strength (C-C bonds) inherent throughout the bulk film, offering superior reliability compared to a 3 nm DLC layer.
Optical Grade SCD (High Purity)	Suitable as a base substrate for epitaxy or complex nano-fabrication.	Ultra-low defect density and exceptional surface smoothness (Ra < 1 nm) crucial for subsequent high-resolution patterning (E-beam lithography) required for nano-tip arrays.
High-Quality PCD Wafers	Suitable for large-area vacuum channel transistor arrays.	Available in large formats (up to 125mm) necessary for device integration and uniformity studies mentioned as an open issue in the paper.

Customization Potential for VCT Development

6CCVD’s advanced processing capabilities ensure that researchers and engineers can acquire materials tailored precisely to the demands of vacuum nanoelectronics, mitigating the risks associated with Si amorphization and electrode instability.

Service Category	6CCVD Capability	Relevance to Research Requirements
Custom Thickness	SCD and PCD thin films from 0.1 µm up to 500 µm. Substrates up to 10 mm.	Allows optimization of film thickness for specific field emission dynamics, stability, and thermal management, replacing the necessity for a 3 nm DLC layer.
Polishing & Surface Quality	SCD polishing to Ra < 1 nm. Inch-size PCD polishing to Ra < 5 nm.	Provides a pristine starting surface essential for precise Si etching or direct diamond tip fabrication, minimizing localized stress points that contribute to material failure.
Advanced Metalization	Standard capabilities including Ti, Pt, Au, Pd, W, Cu deposition (In-house).	Crucial for creating highly robust, low-resistance ohmic contacts or patterned gates necessary for integrated VCT fabrication and improved reliability metrics.
Custom Dimensions	Ability to produce wafers and plates up to 125 mm (PCD) and custom laser cutting for complex geometries.	Facilitates large-scale device integration and array uniformity studies—key challenges identified in the paper.

Engineering Support

This research demonstrates that the interplay between doping, mechanical stress, and surface charge dynamics is critical in high-field, nano-scale devices. 6CCVD’s in-house PhD material science and technical engineering team can assist clients with complex design challenges related to high-frequency and high-power applications, such as vacuum channel transistors (VCTs), field emission display (FED) cathodes, or radiation-hardened electronics.

Our team provides consultation on:

Selecting the optimal SCD or BDD grade to achieve stable, high-current field emission without deformation.
Designing robust diamond structures where the high intrinsic bond strength eliminates the need for stabilizing coatings (like DLC).
Developing metalization stacks optimized for extreme electric fields and vacuum environments.

Call to Action

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For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly. We ship globally (DDU default, DDP available).

Tech Support

Original Source

DOI: https://doi.org/10.1038/srep10631