Parallel Fabrication and Transport Properties of Carbon Nanotube Single Electron Transistors

At a Glance

Metadata	Details
Publication Date	2015-01-01
Journal	STARS (University of Central Florida)
Authors	Muhammad Rakibul Islam
Analysis	Full AI Review Included

Technical Analysis: Scalable Fabrication of Single Electron Transistors (SETs) using Carbon Nanotubes

This technical documentation analyzes a dissertation detailing the scalable, CMOS-compatible fabrication and transport properties of Single Electron Transistors (SETs) utilizing Single-Walled Carbon Nanotubes (SWNTs). The techniques, Dielectrophoresis (DEP) assembly and nanometer-scale barrier formation, present immediate synergies with 6CCVD’s advanced Material Science and CVD Diamond capabilities, particularly for high-frequency, high-power quantum computing and nanoelectronic applications.

Executive Summary

Scalable, CMOS-Compatible Fabrication: Demonstrated a high-yield process (up to 90% assembly yield) for integrating individual SWNTs into device architectures using AC Dielectrophoresis (DEP).
High SET Yield: Achieved an overall SET performance yield of 76% using metal top-contact Schottky barriers (Pd/SWNT interface) for quantum dot (QD) confinement.
Room Temperature Operation: Successfully fabricated SET devices operating up to 285 K by tightly scaling the quantum dot size (L ~40 nm) via a mechanical templating technique (Al/Al₂O₃ local gate).
Quantified Charging Energy: Confirmed single QD behavior at cryogenic temperatures (4.2 K) with charging energies (U_C) of 10-20 meV and up to ~150 meV for RT operation.
Barrier Engineering: Validated two primary methods for tunnel barrier formation: 1) Metal-SWNT Schottky contacts and 2) Mechanical bending over a local gate, proving feasibility across both metallic and semiconducting SWNT types.
Critical Resistance Range: Identified an optimal room temperature contact resistance (R_T) range of 100 KΩ < R_T < 1 MΩ for reproducible single QD SET behavior.

Technical Specifications

The following key physical and electrical performance data points were extracted from the fabrication and measurement chapters:

Parameter	Value	Unit	Context
Max Operating Temperature (SET)	285	K	Achieved via 40 nm mechanical templating
Target Charging Energy (U_C)	~150	meV	Required for 300 K operation (U_C > 4k_BT)
Observed U_C (Single QD, Low T)	10 - 20	meV	R_T range II devices (100 KΩ to 1 MΩ)
QD Length (RT SET - Calculated)	40 - 115	nm	Tuned by mechanical template width
SiO₂ Backgate Thickness	250	nm	Substrate default
Local Gate Dielectric Thickness	2 - 3	nm	Oxygen plasma treated Al₂O₃
Optimal Contact Resistance (R_T)	100 KΩ to 1 MΩ	Ω	Range for reproducible Single QD SET behavior
SET Performance Yield (Top Contact)	75	%	Overall SET yield for 100 nm devices
Individual SWNT Assembly Yield	~23 (Optimized) / 90 (S-rich)	%	DEP assembly yield on 1 µm gaps
Annealing Temperature	200	°C	Used Ar/H₂ mix (1:3 ratio) to reduce R_contact

Key Methodologies

The fabrication process focuses on high-precision lithography and scalable SWNT integration, validating methods critical for post-CMOS nanoelectronics.

Lithography & Patterning:
- Coarse Patterning: Optical lithography used for large Cr (5 nm)/Au (45 nm) contact pads.
- Fine Patterning: Electron Beam Lithography (EBL) utilized to define nanoscale source/drain electrodes (1 µm separation) and ultra-small local gates (~40 nm width).
Metalization Stacks:
- Source/Drain: Cr (3 nm) adhesion layer followed by Pd (25 nm) contact layer.
- Local Gate (Mechanical Template): Cr (2 nm) / Al (18 nm), deposited at liquid nitrogen temperatures to ensure smooth, grain-less film necessary for uniform Al₂O₃ dielectric growth.
Dielectric and Tunnel Barrier Formation:
- Mechanical Template Barrier: Oxygen plasma etching (12-15 minutes) of the Al layer created a thin (2-3 nm) Al₂O₃ local gate dielectric.
- Top-Contact Barrier: Schottky Barriers (SB) formed intrinsically at the Pd/SWNT interface.
SWNT Assembly (Dielectrophoresis - DEP):
- Solution: Stable, surfactant-free aqueous SWNT solution (Brewer Science).
- Optimization: Solution concentration diluted to ~10 ng/mL; AC field applied at 5 V_p-p amplitude and 1 MHz frequency to maximize assembly yield of individual SWNTs.
Characterization and Transport:
- Devices were thermally annealed (200 °C in Ar/H₂) to minimize contact resistance.
- Electron transport measured at cryogenic (4.2 K) and room temperatures (up to 285 K) using a ⁴He cryostat, monitoring Coulomb Blockade (CB) and Coulomb Oscillation (CO) behaviors to extract U_C and quantum dot size.

6CCVD Solutions & Capabilities

The research successfully addresses the complexity of nanoscale device integration. The next logical step for commercialization and extended high-temperature performance (above 300 K) requires substrate materials with superior thermal management, higher dielectric breakdown strength, and ultra-smooth surfaces. 6CCVD’s MPCVD Diamond platforms are uniquely suited to meet these demands.

Applicable Materials for Next-Generation SETs

The performance bottleneck for high-temperature SET operation is the relationship between charging energy (U_C) and thermal energy (k_BT). Achieving operation significantly above 285 K requires substrates optimized for heat dissipation and extremely tight capacitive coupling.

Material Requirement	6CCVD Solution	Technical Advantage
High Thermal Management	Optical Grade SCD (Single Crystal Diamond)	Diamond possesses the highest thermal conductivity (up to 2000 W/m·K), crucial for dissipating heat generated by RTSETs and maximizing k_BT/U_C ratios.
Improved Gate Dielectrics	Boron-Doped Diamond (BDD) thin films	BDD films offer excellent chemical stability and tunable conductivity, potentially serving as a robust, low-loss active gate material replacement for fragile Al/Al₂O₃ stacks.
Nano-Lithography Fidelity	Ultra-Smooth SCD Plates (R_a < 1 nm)	SCD provides the foundation necessary for defining the critical ultra-small features (e.g., < 40 nm local gates) required for high U_C and genuine 300 K+ operation via high-resolution EBL.

Customization Potential

The success of the SWNT SET fabrication hinges on precise control over material dimensions and the delicate electrode contacts. 6CCVD provides the specialized services required to elevate this research to an industrial scale:

Custom Dimensions and Substrate Integration: 6CCVD can supply PCD and SCD plates up to 125 mm in diameter, enabling the large-scale parallel fabrication techniques demonstrated in the paper. We offer substrates up to 10mm thick, providing robust handling capabilities.
Precision Polishing: Our capacity for R_a < 1 nm polishing on SCD ensures an atomically flat foundation, minimizing surface scattering defects that plague solution-processed nanotubes and improving reproducibility of the nanoscale tunnel barriers.
Advanced Metalization Services: The paper utilized Cr/Au and Cr/Pd for contacts and Al/Al₂O₃ for local gates. 6CCVD offers in-house deposition of thin films including Au, Pt, Pd, Ti, W, and Cu, allowing researchers to tune Schottky barrier height or achieve highly ohmic contacts directly on the diamond surface, optimizing charge injection performance.

Engineering Support

This work demonstrates a clear pathway towards SET logic and memory circuits, aligning directly with the objectives of post-CMOS nanoelectronics. 6CCVD’s in-house PhD team provides specialized engineering consultation to assist researchers and engineers leveraging the extraordinary properties of diamond. We specialize in optimizing material selection and interfacing for high-demand quantum projects, including the integration of low-dimensional carbon materials (like SWNTs and Graphene) onto CVD diamond.

For custom specifications or material consultation, visit 6ccvd.com or contact our engineering team directly.

View Original Abstract

Single electron transistors (SET) have attracted significant attention as a potential building block for post CMOS nanoelectronic devices. However, lack of reproducible and parallel fabrication approach and room temperature operation are the two major bottlenecks for practical realization of SET based devices. In this thesis, I demonstrate large scale single electron transistors fabrication techniques using solution processed single wall carbon nanotubes (SWNTs) and studied their electron transport properties. The approach is based on the assembly of individual SWNTs via dielectrophoresis (DEP) at the selected position of the circuit and formation of tunnel barriers on SWNT. Two different techniques: i) metal-SWNT Schottky contact, and ii) mechanical templating of SWNTs were used for tunnel barrier creation. Low temperature (4.2K) transport measurement of 100 nm long metal-SWNT Schottky contact devices show that 93% of the devices with contact resistance (RT) > 100 K? show SET behavior. Majority (90%) of the devices with 100 K? < RT < 1 M?, show periodic, well-de?ned Coulomb diamonds with a charging energy ~ 15 meV, represents single electron tunnelling through a single quantum dot (QD), defined by the top contact. For high RT (> 1M?), devices show multiple QDs behaviors, while QD was not formed for low RT ( < 100 K?) devices. From the transport study of 50 SWNT devices, a total of 38 devices show SET behavior giving an yield of 76%. I also demonstrate room temperature operating SET by using mechanical template technique. In mechanical template method individual SWNT is placed on top of a Al/Al2O3 local gate which bends the SWNT at the edge and tunnel barriers are created. SET devices fabricated with a template width of ~20 nm shows room temperature operation with a charging energy of ~150 meV. I also discussed the detailed transport spectroscopy of the devices.

Tech Support

Original Source

DOI: None